N. Ito, H. Komatsu, A. Kanuma, Akihiro Yoshitake, Yoshiyasu Tanamura, H. Sugiyama, R. Yamashita, Ken-ichi Nabeya, H. Yoshino, H. Yamanaka, Masahiro Yanagida, Yoshitomo Ozeki, Kinya Ishizaka, Takeshi Kono, Yutaka Isoda
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Design Methodology for 2.4GHz Dual-Core Microprocessor
This paper presents a design methodology that was applied to the design of a 2.4GHz dual-core SPARC64trade microprocessor with 90nm CMOS technology. It focuses on the newly adopted techniques, such as efficient data management in dual-core design, fast delay calculation of the noise-immune clock distribution circuit, enhanced signal integrity analysis of a large-scale custom macro design, and enhanced diagnosis capability using a logic BIST circuit.
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