Numerical Function Generators Using Edge-Valued Binary Decision Diagrams

Shinobu Nagayama, Tsutomu Sasao, J. T. Butler
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引用次数: 6

Abstract

In this paper, we introduce the edge-valued binary decision diagram (EVBDD) to reduce the memory and delay in numerical function generators (NFGs). An NFG realizes a function, such as a trigonometric, logarithmic, square root, or reciprocal function, in hardware. NFGs are important in, for example, digital signal applications, where high speed and accuracy are necessary. We use the EVBDD to produce a fast and compact segment index encoder (SIE) that is a key component in our NFG. We compare our approach with NFG designs based on multi-terminal BDDs (MTBDDs), and show that the EVBDD produces SIEs that have, on average, only 7% of the memory and 40% of the delay of those designed using MTBDDs. Therefore, our NFGs based on EVBDDs have, on average, only 38% of the memory and 59% of the delay of NFGs based on MTBDDs.
使用边值二值决策图的数值函数生成器
本文引入边值二值决策图(EVBDD)来减少数值函数生成器(NFGs)的内存和延迟。NFG在硬件上实现一个函数,如三角函数、对数函数、平方根函数或倒数函数。例如,NFGs在需要高速和精度的数字信号应用中非常重要。我们使用EVBDD来生产快速紧凑的片段索引编码器(SIE),这是我们NFG的关键组件。我们将我们的方法与基于多终端bdd (mtbdd)的NFG设计进行了比较,结果表明,EVBDD产生的si平均只有使用mtbdd设计的si的7%的内存和40%的延迟。因此,我们基于evbdd的nfg平均只有基于mtbdd的nfg的38%的内存和59%的延迟。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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