Design Methodology for 2.4GHz Dual-Core Microprocessor

N. Ito, H. Komatsu, A. Kanuma, Akihiro Yoshitake, Yoshiyasu Tanamura, H. Sugiyama, R. Yamashita, Ken-ichi Nabeya, H. Yoshino, H. Yamanaka, Masahiro Yanagida, Yoshitomo Ozeki, Kinya Ishizaka, Takeshi Kono, Yutaka Isoda
{"title":"Design Methodology for 2.4GHz Dual-Core Microprocessor","authors":"N. Ito, H. Komatsu, A. Kanuma, Akihiro Yoshitake, Yoshiyasu Tanamura, H. Sugiyama, R. Yamashita, Ken-ichi Nabeya, H. Yoshino, H. Yamanaka, Masahiro Yanagida, Yoshitomo Ozeki, Kinya Ishizaka, Takeshi Kono, Yutaka Isoda","doi":"10.1109/ASPDAC.2007.358103","DOIUrl":null,"url":null,"abstract":"This paper presents a design methodology that was applied to the design of a 2.4GHz dual-core SPARC64trade microprocessor with 90nm CMOS technology. It focuses on the newly adopted techniques, such as efficient data management in dual-core design, fast delay calculation of the noise-immune clock distribution circuit, enhanced signal integrity analysis of a large-scale custom macro design, and enhanced diagnosis capability using a logic BIST circuit.","PeriodicalId":362373,"journal":{"name":"2007 Asia and South Pacific Design Automation Conference","volume":"101 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 Asia and South Pacific Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.2007.358103","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

This paper presents a design methodology that was applied to the design of a 2.4GHz dual-core SPARC64trade microprocessor with 90nm CMOS technology. It focuses on the newly adopted techniques, such as efficient data management in dual-core design, fast delay calculation of the noise-immune clock distribution circuit, enhanced signal integrity analysis of a large-scale custom macro design, and enhanced diagnosis capability using a logic BIST circuit.
2.4GHz双核微处理器的设计方法
本文提出了一种基于90nm CMOS技术的2.4GHz双核SPARC64trade微处理器的设计方法。它重点介绍了新采用的技术,如双核设计中的高效数据管理,抗噪声时钟分配电路的快速延迟计算,大规模定制宏设计的增强信号完整性分析,以及使用逻辑BIST电路的增强诊断能力。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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