Architectural Optimizations for Text to Speech Synthesis in Embedded Systems

Abstract

The increasing processing power of embedded devices have created the scope for certain applications that could previously be executed in desktop environments only, to migrate into handheld platforms. An important feature of the computing systems of modern times is their support for applications that interact with the user by synthesizing natural speech output. Such applications deliver state of the art performance in desktop environments. However, the real-time performance of such applications in handheld platforms with on-line incoming text streams have not been explored till date. In this work, the performance of a text to speech synthesis application is evaluated on embedded processor architectures and modifications in the underlying hardware platform are proposed for real time performance improvement of the concerned application.