Exploration of Low Power Adders for a SIMD Data Path

Giacomo Paci, P. Marchal, L. Benini
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引用次数: 2

Abstract

Hardware for ambient intelligence needs to achieve extremely high computational efficiency (up to 40GOPS/W). An important way for reaching this is exploiting parallelism, and more specifically data-level parallelism enabled by SIMD. Whereas a large body of research exists on the benefits of the architectural design of and compilation onto SIMD, the design of energy-optimal functional units for SIMD has received limited attention. It appears that existing SIMD functional units are designed in an area optimal, but not energy optimal way. By exploiting the difference in critical path length for the types of operations (e.g., 4times8/2times16/1times32), SIMD adders can be developed that save up to 40% of energy. In this paper, the authors present these adders, the issues of building them and quantify their benefits for different usage scenarios and operating frequencies.
SIMD数据路径低功耗加法器的探索
环境智能硬件需要达到极高的计算效率(高达40GOPS/W)。实现这一目标的一个重要方法是利用并行性,更具体地说,是SIMD支持的数据级并行性。尽管对SIMD的架构设计和编译的好处进行了大量的研究,但SIMD的能量最优功能单元的设计却受到了有限的关注。现有SIMD功能单元的设计思路是面积最优,而不是能量最优。通过利用不同类型操作的关键路径长度的差异(例如,4times8/2times16/1times32), SIMD加法器可以节省高达40%的能量。在本文中,作者介绍了这些加法器,构建它们的问题,并量化了它们在不同使用场景和工作频率下的好处。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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