{"title":"Time partitioning framework for partially reconfigurable systems","authors":"A. Mtibaa, B. Ouni, M. Abid","doi":"10.1109/ICM.2004.1434206","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434206","url":null,"abstract":"The FPGAs architectures allow the overlap between execution and reconfiguration. Indeed, fractions of the application can be configured at the same time that others fractions of the application can be executed. This approach is called partially reconfiguration that used for partially reconfigurable FPGAs. The partially reconfiguration approach can be used to fit a large application into the FPGA device by partitioning the application over time. At each partition, set of tasks are configured and other sets of tasks are executed. This partitioning over time of execution and configuration of tasks is achieved so that the latency of the application is optimal. In this paper, we introduce a time partitioning and a design flow approach for partially reconfigurable systems.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121011844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"VLSI architecture of Rayleigh fading simulator based on IIR filter and polyphase interpolator","authors":"F. Sattar, M. Mufti","doi":"10.1109/ICM.2004.1434270","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434270","url":null,"abstract":"This paper presents hardware design of a Rayleigh fading simulator that efficiently generates Gaussian variates with Jakes power spectral density. The architecture is based on Komninakis design consisting of a fixed IIR filter followed by a polyphase interpolator for different Doppler rates. The hardware simulator facilitates real time error performance evaluation of wireless channels in Rayleigh fading environments. It also offers the potential of improving the evaluation speed by orders of magnitude over a software based simulation.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123995231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Black box representation of electronic equipments for EMI simulation: a physical approach","authors":"M. Hamzaoui, P. Besnier, M. Drissi","doi":"10.1109/ICM.2004.1434700","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434700","url":null,"abstract":"An entirely computational based analysis of electromagnetic interference (EMI) produced by a set of electronic equipments appears extremely difficult to achieve. The present work proposes an approach aiming at modeling equipments as a black box including appropriate excitation sources. Each source is associated with the experimental identification of radiation paths. The obtained results are compared to measurements and show a good agreement.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127944270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 2.4 GHz RF CMOS receiver for low cost digital wireless communication for 802.15.4 standard","authors":"M. Egels, J. Gaubert, P. Pannier, G. Bas","doi":"10.1109/ICM.2004.1434272","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434272","url":null,"abstract":"Feasibility of 2.4 GHz RF CMOS receiver for low cost digital wireless communication for the 802.15.4 standard is demonstrated. The LNA, switch, and mixer architecture and design are described in the context of low cost and low power CMOS integrated circuits. Simulations with 0.28 /spl mu/m design kit shown 5 dB noise figure and 36 dB voltage gain for less than 30 mW power consumption. Additional considerations based on EM simulations to minimize substrate coupling and to avoid high frequency parasitic effects are also presented.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127596380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Mahamdi, F. Mansour, P. Temple-Boyer, E. Scheid
{"title":"Effect of nitrogen on the diffusion and the activation of the boron implanted in polysilicon thin layers","authors":"R. Mahamdi, F. Mansour, P. Temple-Boyer, E. Scheid","doi":"10.1109/ICM.2004.1434728","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434728","url":null,"abstract":"This work deals with the study of polysilicon thin layers doped in-situ with nitrogen, know as nitrogen doped silicon (NIDOS), strongly doped boron. These films are used in microelectronics technology as P+ MOS transistors gates, etc. The study of nitrogen effect on the redistribution and the activation of boron during annealing in NIDOS film is necessary. These films were deposited by low pressure chemical vapor deposition using a mixture of disilane and of ammonia, with a nitrogen content, varying from 0 to 16%. The study of secondary ion mass spectrometry (SIMS) profiles showed that the boron diffusion is reduced with increasing nitrogen ratio. The resistivity of films increases with increasing nitrogen ratio. The surface roughness measurement illustrates that the initially amorphous films present a smooth surface, but after annealing the roughness is about some nanometers. Finally, scanning electron microscope (SEM) observations showed a significant crystallization of the films without nitrogen, annealed at 850/spl deg/C/15 min. Whereas, films with weak nitrogen content, annealed at 1050/spl deg/C/15 min showed a start of crystallization. We can note that the obtained results by various characterizations are in good agreement for the reduction of the boron diffusion and the crystallization of deposits during thermal annealing.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128762206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Accelerating equalization algorithms using the Xtensa configurable processor","authors":"B. Tanguay, Y. Savaria, M. Sawan","doi":"10.1109/ICM.2004.1434607","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434607","url":null,"abstract":"This paper deals with the design and implementation of two equalizers for telecommunications applications. The required performance cannot be achieved using general-purpose embedded processors. On the other hand, application specific instruction-set processors (ASIP) allow accelerating sections of code, which helps reaching the required performance. This paper considers two equalizers: a linear transversal equalizer (LTE) and a decision feedback equalizer (DFE). Means of accelerating the LTE and DFE algorithms are considered. It is demonstrated, using Tensilica technology, that it is possible to improve performance of these cores by a factor of 17 for the LTE and 22 for the DFE. These improvements result from addition of specialized instructions that parallelize repetitive operations.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129191654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Transient current testing of dynamic CMOS circuits in the presence of leakage and process variation","authors":"A. Chehab, A. Kayssi, A. Nazer, N. Aaraj","doi":"10.1109/ICM.2004.1434593","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434593","url":null,"abstract":"We propose a method for testing dynamic CMOS circuits using the transient power supply current, i/sub DDT/. The method is based on setting the primary inputs of the circuit under test, switching the clock signal and monitoring the peak magnitude of i/sub DDT/. If the magnitude lies outside a predetermined range, a defect is inferred. We target resistive open defects that can either cause the circuit to fail, or introduce unacceptable delay and hence result in degraded circuit performance. We propose two methods for generating test vectors for i/sub DDT/ testing. One method is based on random vector generation while the second uses a SAT-solver. Fault simulation results on domino CMOS circuits show a high rate of detection for resistive open faults that cannot be otherwise detected using the traditional voltage or I/sub DDQ/ testing. We also show that by using a normalization procedure, the defects can be detected with a single threshold setup in the presence of leakage and process variations that normally hinder the detection capability of current-based testing techniques.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133516967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"HW-SW design methodologies used for a MPEG video compressor synthesis","authors":"A. Portero, O. Navas, J. Carrabina","doi":"10.1109/ICM.2004.1434777","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434777","url":null,"abstract":"In the last years many new concepts appeared for the system design, with the so-called HW/SW co-design based on system (SoC) and virtual components. Those concepts rely to methodologies that try to integrate HW and SW design techniques in just one consistent system-level methodology allowing to work in a way that is more secure (specifications and developments are verifiable), more efficient (cost analysable) and can be automated (through systems synthesis). A MPEG demonstrator based on video compression has been designed and validated. It implements video coding using the standard ISO/IEC 13818-2 | ITU-T H.262H (also know as \"MPEG2 video\"), for the main profile and main level (720/spl times/480, 30 fps). The encoder implements frames I or I-pictures. It has been developed a MPEG compressor based on DCT (discrete cosine transform) through two different methodologies. First one, it is based in Matlab DSP builder from Altera that is a down up methodology, based on component instantiation. And the other, it is a top down methodology based on behavioural SystemC description and synthesized with SystemC behavioural compiler from synopsys.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133582752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"System design challenges in ubiquitous computing environments","authors":"M. Glesner, T. Hollstein, T. Murgan","doi":"10.1109/ICM.2004.1434192","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434192","url":null,"abstract":"Improved micro- and nanoelectronics technologies are the enabling factor for new embedded computing products, which can be smoothly integrated into living and working environments. Computing becomes ubiquitous and requires more flexibility than previous generations of computing devices. Changing environments and evolving standards imply the need of system adaption. Moreover, ubiquitous computing devices should be able to adapt to different application patterns and user profiles. Scalability is an important issue, allowing functional extensions to already deployed systems. In this contribution, we give an overview on the characteristics of ubiquitous computing environments. Furthermore, we address future micro- and nanoelectronics design challenges for embedded systems-on-chip.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127005021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Asynchronous packet-switch for SoC","authors":"Jun Xu, R. Sotudeh","doi":"10.1109/ICM.2004.1434580","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434580","url":null,"abstract":"System-on-chip (SoC) design is facing increasing difficulties in its integration, global wiring delay and power dissipation. Interconnection network technology has the advantage over the conventional bus technology in its scalability; on the other hand, asynchronous circuit design technology may offer power saving and tackle the clock-skew problem. The combination of these two technologies therefore could be an optimal solution for the interconnection of SoC. In this paper, we focus on the implementation of packet-switch with asynchronous technology. The results of experiments run to evaluate several aspects of the packet-switch implementation are presented.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131670126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}