Accelerating equalization algorithms using the Xtensa configurable processor

Abstract

This paper deals with the design and implementation of two equalizers for telecommunications applications. The required performance cannot be achieved using general-purpose embedded processors. On the other hand, application specific instruction-set processors (ASIP) allow accelerating sections of code, which helps reaching the required performance. This paper considers two equalizers: a linear transversal equalizer (LTE) and a decision feedback equalizer (DFE). Means of accelerating the LTE and DFE algorithms are considered. It is demonstrated, using Tensilica technology, that it is possible to improve performance of these cores by a factor of 17 for the LTE and 22 for the DFE. These improvements result from addition of specialized instructions that parallelize repetitive operations.