Transient current testing of dynamic CMOS circuits in the presence of leakage and process variation

Abstract

We propose a method for testing dynamic CMOS circuits using the transient power supply current, i/sub DDT/. The method is based on setting the primary inputs of the circuit under test, switching the clock signal and monitoring the peak magnitude of i/sub DDT/. If the magnitude lies outside a predetermined range, a defect is inferred. We target resistive open defects that can either cause the circuit to fail, or introduce unacceptable delay and hence result in degraded circuit performance. We propose two methods for generating test vectors for i/sub DDT/ testing. One method is based on random vector generation while the second uses a SAT-solver. Fault simulation results on domino CMOS circuits show a high rate of detection for resistive open faults that cannot be otherwise detected using the traditional voltage or I/sub DDQ/ testing. We also show that by using a normalization procedure, the defects can be detected with a single threshold setup in the presence of leakage and process variations that normally hinder the detection capability of current-based testing techniques.