{"title":"HW-SW design methodologies used for a MPEG video compressor synthesis","authors":"A. Portero, O. Navas, J. Carrabina","doi":"10.1109/ICM.2004.1434777","DOIUrl":null,"url":null,"abstract":"In the last years many new concepts appeared for the system design, with the so-called HW/SW co-design based on system (SoC) and virtual components. Those concepts rely to methodologies that try to integrate HW and SW design techniques in just one consistent system-level methodology allowing to work in a way that is more secure (specifications and developments are verifiable), more efficient (cost analysable) and can be automated (through systems synthesis). A MPEG demonstrator based on video compression has been designed and validated. It implements video coding using the standard ISO/IEC 13818-2 | ITU-T H.262H (also know as \"MPEG2 video\"), for the main profile and main level (720/spl times/480, 30 fps). The encoder implements frames I or I-pictures. It has been developed a MPEG compressor based on DCT (discrete cosine transform) through two different methodologies. First one, it is based in Matlab DSP builder from Altera that is a down up methodology, based on component instantiation. And the other, it is a top down methodology based on behavioural SystemC description and synthesized with SystemC behavioural compiler from synopsys.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"279 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2004.1434777","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
In the last years many new concepts appeared for the system design, with the so-called HW/SW co-design based on system (SoC) and virtual components. Those concepts rely to methodologies that try to integrate HW and SW design techniques in just one consistent system-level methodology allowing to work in a way that is more secure (specifications and developments are verifiable), more efficient (cost analysable) and can be automated (through systems synthesis). A MPEG demonstrator based on video compression has been designed and validated. It implements video coding using the standard ISO/IEC 13818-2 | ITU-T H.262H (also know as "MPEG2 video"), for the main profile and main level (720/spl times/480, 30 fps). The encoder implements frames I or I-pictures. It has been developed a MPEG compressor based on DCT (discrete cosine transform) through two different methodologies. First one, it is based in Matlab DSP builder from Altera that is a down up methodology, based on component instantiation. And the other, it is a top down methodology based on behavioural SystemC description and synthesized with SystemC behavioural compiler from synopsys.