2006 IEEE International Conference on Field Programmable Technology最新文献_第3页

Hardware join Java: a unified hardware/software language for dynamic partial runtime reconfigurable computing applications 硬件连接Java:用于动态部分运行时可重构计算应用程序的统一硬件/软件语言

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270327

D. Kearney, John Hopf

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引用次数: 1

FPGA acceleration of the tate pairing in characteristic 2 特性2中状态对的FPGA加速

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270314

Robert Ronan, Colm O'hEigeartaigh, Colin C. Murphy, M. Scott, T. Kerins

引用次数: 23

FPGA-based MSB-first bit-serial variable block size motion estimation processor 基于fpga的MSB-first bit-serial可变块大小运动估计处理器

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270308

Brian M. H. Li, P. Leong

引用次数: 5

Hardware architectures for Monte-Carlo based financial simulations 基于蒙特卡罗的金融模拟的硬件架构

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270352

David B. Thomas, Jacob A. Bower, W. Luk

引用次数: 21

A C compiler for implementing FPGA based bit-serial DSP systems 实现基于FPGA的位串行DSP系统的C编译器

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270334

D. Cyca, L. Turner

引用次数: 1

Dynamically reconfigurable protocol transducer 动态可重构协议传感器

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270343

Shota Watanabe, Yuji Ishikawa, Kenshu Seto, S. Komatsu, M. Fujita

引用次数: 0

Granularity aspects for the design of multi-level reconfigurable architectures 多级可重构架构设计的粒度方面

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270385

S. Lange, M. Middendorf

{"title":"Granularity aspects for the design of multi-level reconfigurable architectures","authors":"S. Lange, M. Middendorf","doi":"10.1109/FPT.2006.270385","DOIUrl":"https://doi.org/10.1109/FPT.2006.270385","url":null,"abstract":"Dynamically reconfigurable hardware has already been deployed for accelerating computationally demanding applications. Some of these hardware architectures allow run time reconfiguration but this leads usually to a large reconfiguration overhead. The advantage of run time reconfiguration is that it allows new algorithmic solutions for many applications. To study the potential of frequent run time reconfiguration it is interesting to investigate its costs and benefits from an abstract point of view and to develop new architectural concepts. Multilevel reconfigurable architectures are one such concept that introduce several levels of reconfiguration. This paper deals with new types of multi-level reconfigurable architectures. The corresponding problem of finding the best granularity for different reconfiguration levels is formulated and investigated. Although this problem is shown to be NP-complete, an interesting restricted subcase is solved optimally in polynomial time. For the general case, a good heuristic is proposed that is based on solutions for the restricted case. Results on three example applications show that the reconfiguration cost can be reduced with the new architectures. Based on a proposed measure of relative efficiency it is also shown that the new architectures are more efficient so that they obtain a larger reconfiguration cost reduction with less additional hardware","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126752546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Super fast hardware string matching 超级快速的硬件字符串匹配

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270354

D. Lo, Yi-Gang Tai, K. Psarris, Wen-Jyi Hwang

引用次数: 7

Design and validation of execution schemes for dynamically reconfigurable architectures 动态可重构体系结构执行方案的设计与验证

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270346

Tobias Oppold, Sven Eisenhardt, W. Rosenstiel

引用次数: 4

A highly parameterizable parallel processor array architecture 一个高度可参数化的并行处理器阵列架构

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270293

D. Kissler, Frank Hannig, A. Kupriyanov, J. Teich

引用次数: 91