基于fpga的MSB-first bit-serial可变块大小运动估计处理器

Brian M. H. Li, P. Leong
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引用次数: 5

摘要

H.264/AVC是最新的视频编码标准,采用可变块大小、四分之一像素精度、运动矢量预测和多参考帧进行运动估计。这些新特性导致比以前的编码标准更高的计算需求。本文提出了一种新的最有效位(MSB)首位串行结构,用于全搜索块匹配(FSBM)可变块大小运动估计。由于msb优先处理的性质允许提前终止绝对差和(SAD)计算,因此可以提高平均硬件性能。该体系结构在Xilinx Virtex-II XC2V6000 FPGA上进行了仿真、综合和实现。在-16到15个搜索范围内,实现的最大频率为340 MHz,吞吐量约为每秒18674个宏块。资源利用率为3345lut,可对CIF分辨率视频进行实时编码
本文章由计算机程序翻译,如有差异,请以英文原文为准。
FPGA-based MSB-first bit-serial variable block size motion estimation processor
H.264/AVC is the latest video coding standard adopting variable block size, quarter-pixel accuracy, motion vector prediction and multi-reference frames for motion estimation. These new features result in much higher computation requirements than previous coding standards. In this paper we propose a novel most significant bit (MSB) first bit-serial architecture for full-search block matching (FSBM) variable block size motion estimation. Since the nature of MSB-first processing enables early termination of the sum of absolute difference (SAD) calculation, the average hardware performance can be enhanced. The architecture has been simulated, synthesized and implemented on a Xilinx Virtex-II XC2V6000 FPGA. The maximum frequency achieved is 340 MHz and the throughput rate is around 18674 macroblocks per second within a -16 to 15 search range. The resource utilization is 3345 LUTs and it can encode CIF resolution video in real time
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