{"title":"基于fpga的MSB-first bit-serial可变块大小运动估计处理器","authors":"Brian M. H. Li, P. Leong","doi":"10.1109/FPT.2006.270308","DOIUrl":null,"url":null,"abstract":"H.264/AVC is the latest video coding standard adopting variable block size, quarter-pixel accuracy, motion vector prediction and multi-reference frames for motion estimation. These new features result in much higher computation requirements than previous coding standards. In this paper we propose a novel most significant bit (MSB) first bit-serial architecture for full-search block matching (FSBM) variable block size motion estimation. Since the nature of MSB-first processing enables early termination of the sum of absolute difference (SAD) calculation, the average hardware performance can be enhanced. The architecture has been simulated, synthesized and implemented on a Xilinx Virtex-II XC2V6000 FPGA. The maximum frequency achieved is 340 MHz and the throughput rate is around 18674 macroblocks per second within a -16 to 15 search range. The resource utilization is 3345 LUTs and it can encode CIF resolution video in real time","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"186 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"FPGA-based MSB-first bit-serial variable block size motion estimation processor\",\"authors\":\"Brian M. H. Li, P. Leong\",\"doi\":\"10.1109/FPT.2006.270308\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"H.264/AVC is the latest video coding standard adopting variable block size, quarter-pixel accuracy, motion vector prediction and multi-reference frames for motion estimation. These new features result in much higher computation requirements than previous coding standards. In this paper we propose a novel most significant bit (MSB) first bit-serial architecture for full-search block matching (FSBM) variable block size motion estimation. Since the nature of MSB-first processing enables early termination of the sum of absolute difference (SAD) calculation, the average hardware performance can be enhanced. The architecture has been simulated, synthesized and implemented on a Xilinx Virtex-II XC2V6000 FPGA. The maximum frequency achieved is 340 MHz and the throughput rate is around 18674 macroblocks per second within a -16 to 15 search range. The resource utilization is 3345 LUTs and it can encode CIF resolution video in real time\",\"PeriodicalId\":354940,\"journal\":{\"name\":\"2006 IEEE International Conference on Field Programmable Technology\",\"volume\":\"186 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE International Conference on Field Programmable Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FPT.2006.270308\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Conference on Field Programmable Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FPT.2006.270308","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
H.264/AVC is the latest video coding standard adopting variable block size, quarter-pixel accuracy, motion vector prediction and multi-reference frames for motion estimation. These new features result in much higher computation requirements than previous coding standards. In this paper we propose a novel most significant bit (MSB) first bit-serial architecture for full-search block matching (FSBM) variable block size motion estimation. Since the nature of MSB-first processing enables early termination of the sum of absolute difference (SAD) calculation, the average hardware performance can be enhanced. The architecture has been simulated, synthesized and implemented on a Xilinx Virtex-II XC2V6000 FPGA. The maximum frequency achieved is 340 MHz and the throughput rate is around 18674 macroblocks per second within a -16 to 15 search range. The resource utilization is 3345 LUTs and it can encode CIF resolution video in real time