2006 IEEE International Conference on Field Programmable Technology最新文献

FPGA implementation of tabu search for the quadratic assignment problem 用FPGA实现禁忌搜索的二次分配问题

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270325

S. Wakabayashi, Yoshihiro Kimura, Shinobu Nagayama

引用次数: 7

Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters 利用阴影簇提高硬电路fpga的面积效率

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270384

P. Jamieson, Jonathan Rose

{"title":"Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters","authors":"P. Jamieson, Jonathan Rose","doi":"10.1109/FPT.2006.270384","DOIUrl":"https://doi.org/10.1109/FPT.2006.270384","url":null,"abstract":"There is a dramatic logic density gap between FPGAs and ASICs, and this gap is the main reason FPGAs are not cost-effective in high volume applications. Modern FPGAs narrow this gap by including \"hard\" circuits such as memories and multipliers, which are very efficient when they are used. However, if these hard circuits are not used, they go wasted (including the very expensive programmable routing that surrounds the logic) and have a negative impact on logic density. In this paper we propose a new architectural concept, called shadow clusters, that seeks to mitigate this loss. A shadow cluster is a standard FPGA logic \"cluster\" that is placed \"behind\" every hard circuit and can programmably, through simple, small multiplexers, replace the hard circuit in the event it isn't needed. The authors measure the area-efficiency of FPGAs with and without shadow clusters and show that a modern commercial architecture (with a fixed ratio of multipliers to soft logic) would gain 4.7% in area-efficiency by employing shadow clusters. Indeed, every architecture we studied under \"reasonable\" conditions never showed a loss of area-efficiency. Furthermore, we show that most area-efficient architecture that employs the shadow cluster concept is 12.5 % better than the most area-efficient architecture without shadow clusters","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121913331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 41

Hardware channel model for ultra wideband systems 超宽带系统的硬件信道模型

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270332

Wen-Chih Kan, G. Sobelman

引用次数: 2

An adaptive Viterbi decoder on the dynamically reconfigurable processor 基于动态可重构处理器的自适应维特比解码器

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270329

Shohei Abe, Y. Hasegawa, T. Toi, Takeshi Inuo, H. Amano

引用次数: 5

Perturber: semi-synthetic circuit generation using ancestor control for testing incremental place and route 摄动器:半合成电路生成使用祖先控制测试增量位置和路线

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270311

D. Grant, G. Lemieux

引用次数: 6

An FPGA-based floating-point processor array supporting a high-precision dot product 一种支持高精度点积的基于fpga的浮点处理器阵列

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270337

F. Mayer-Lindenberg, Valerij Beller

引用次数: 10

A real time programmable encoder for low density parity check code targeting a reconfigurable instruction cell architecture 针对可重构指令单元结构的低密度奇偶校验码的实时可编程编码器

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270319

Zahid Khan, T. Arslan

引用次数: 3

Implementation of a real-time multiple input multiple output channel estimator on the smart antenna software radio test system platform using the Xilinx Virtex 2 Pro Field Programmable Gate Array 利用Xilinx Virtex 2 Pro现场可编程门阵列在智能天线软件无线电测试系统平台上实现实时多输入多输出信道估计器

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270322

P. J. Green, Desmond P. Taylor

引用次数: 3

FADES: a fault emulation tool for fast dependability assessment 用于快速可靠性评估的故障仿真工具

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270315

D. Andrés, Juan-Carlos Ruiz-Garcia, D. Gil, P. Gil

引用次数: 11

An adaptive frequency control method using thermal feedback for reconfigurable hardware applications 一种用于可重构硬件应用的热反馈自适应频率控制方法

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270316

Phillip H. Jones, Young-Hee Cho, J. Lockwood

{"title":"An adaptive frequency control method using thermal feedback for reconfigurable hardware applications","authors":"Phillip H. Jones, Young-Hee Cho, J. Lockwood","doi":"10.1109/FPT.2006.270316","DOIUrl":"https://doi.org/10.1109/FPT.2006.270316","url":null,"abstract":"Reconfigurable circuits running in field programmable gate arrays (FPGAs) can be dynamically optimized for power based on computational requirements and thermal conditions of the environment. In the past, FPGA circuits were typically small and operated at a low frequency. Few users were concerned about high-power consumption and the heat generated by FPGA devices. The current generation of FPGAs, however, use extensive pipelining techniques to achieve high data processing rates and dense layouts that can generate significant amounts of heat. FPGA circuits can be synthesized that can generate more heat than the package can dissipate. For FPGAs that operate in controlled environments, heatsinks and fans can be mounted to the device to extract heat from the device. When FPGA devices do not operate in a controlled environment, however, changes to ambient temperature due to factors such as the failure of a fan or a reconfiguration of bitfile running on the device can drastically change the operating conditions. A protection mechanism is needed to ensure the proper operation of the FPGA circuits when such a change occurs. To address these issues, we have devised a reconfigurable temperature monitoring system that gives feedback to the FPGA circuit using the measured junction temperature of the device. Using this feedback, we designed a novel dual frequency switching system that allows the FPGA circuits to maintain the highest level of performance for a given maximum junction temperature. Our working system has been implemented and deployed on the field programmable port extender (FPX) platform at Washington University in St. Louis. Our experimental results with a scalable image correlation circuit show up to a 2.4times factor increase in performance as compared to a system without thermal feedback. Our circuit ensures that the device performs the maximum required computation while always operating within a safe temperature range","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121259256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11