A real time programmable encoder for low density parity check code targeting a reconfigurable instruction cell architecture

Abstract

This paper presents a new real time programmable irregular low density parity check (LDPC) encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for frame sizes from 576 to 2304 and for five different code rates. H matrix is efficiently generated and stored for a particular frame size and code rate. The encoder is implemented on reconfigurable instruction cell based architecture which has recently emerged as an ultra low power, high performance, ANSI-C programmable embedded core. Different general and technology specific optimization techniques are applied in order to achieve a throughput, ranging from 10 to 19 Mbps