2006 IEEE International Conference on Field Programmable Technology最新文献_第2页

Optimal set of body bias voltages for an FPGA with field-programmable V/sub th/ components 具有现场可编程V/sub /元件的FPGA的最佳体偏置电压集

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270340

Takashi Kawanami, M. Hioki, Y. Matsumoto, T. Tsutsumi, T. Nakagawa, T. Sekigawa, H. Koike

{"title":"Optimal set of body bias voltages for an FPGA with field-programmable V/sub th/ components","authors":"Takashi Kawanami, M. Hioki, Y. Matsumoto, T. Tsutsumi, T. Nakagawa, T. Sekigawa, H. Koike","doi":"10.1109/FPT.2006.270340","DOIUrl":"https://doi.org/10.1109/FPT.2006.270340","url":null,"abstract":"An FPGA with field-programmable Vth components can attain both high performance and low power consumption, without placement and routing constraints, by flexibly controlling the threshold voltage (Vth) of transistors. Since Vth for transistors for a specific circuit block in an FPGA is chosen from a set of Vth values defined by body bias voltage set (BBVS), adequate selection of BBVS is important in the design decision process in a field-programmable Vth method. In this paper, the effect of the selection of BBVS on static power reduction in an FPGA with field-programmable Vth components was presented. To select the optimal BBVS among several supplied body bias voltage candidates, several BBVSs are provided. The results show that the best BBVS achieves remarkable static power reduction, to as little as 1/30 the value in a conventional FPGA without performance degradation. In addition, the study on the optimal selection of body bias voltage for high-Vth transistor in a BBVS reveals that deep reverse body bias for high-Vth transistor does not necessarily offer the optimal condition, and optimization is necessary","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114850100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

FPGA implementation for an iris biometric processor 虹膜生物识别处理器的FPGA实现

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270324

J. Liu-Jimenez, R. Sánchez-Reillo, A. Lindoso, O. Miguel-Hurtado

引用次数: 18

Multithreaded virtual-memory-enabled reconfigurable hardware accelerators 支持多线程虚拟内存的可重构硬件加速器

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270312

M. Vuletic, P. Ienne, Christopher Claus, W. Stechele

{"title":"Multithreaded virtual-memory-enabled reconfigurable hardware accelerators","authors":"M. Vuletic, P. Ienne, Christopher Claus, W. Stechele","doi":"10.1109/FPT.2006.270312","DOIUrl":"https://doi.org/10.1109/FPT.2006.270312","url":null,"abstract":"Although naturally belonging to the user process, hardware parts of codesigned reconfigurable applications execute outside of the operating system (OS) process: they have neither unified memory abstraction with software nor system services provided by the OS. This imposes limitations on hardware and software interfacing, narrows available programming paradigms, and affects application portability. Advanced programming concepts, such as multithreading, usually demand additional activities on the programmer side, to perform memory transfers and enforce memory consistency. In this paper, we introduce a system layer (an OS extension relying on a system hardware extension) that provides: (1) unified virtual memory, (2) platform-agnostic interfacing, and (3) multithreaded execution, for hardware accelerators running within the same OS process with user software. The system layer releases software programmer and hardware designer from interfacing burdens and, still, achieves significant speedups over software with only limited overheads. Virtual-memory-enabled hardware accelerators benefit from all abstractions and services already available to software. To prove our concept in practice and demonstrate the ease of programming, we execute image processing and cryptography applications on reconfigurable systems-on-chip running GNU/Linux that supports virtual memory for multithreaded hardware accelerators","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124859210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A statistical framework for dimensionality reduction implementation in FPGAs fpga降维实现的统计框架

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270349

C. Bouganis, I. Pournara, P. Cheung

{"title":"A statistical framework for dimensionality reduction implementation in FPGAs","authors":"C. Bouganis, I. Pournara, P. Cheung","doi":"10.1109/FPT.2006.270349","DOIUrl":"https://doi.org/10.1109/FPT.2006.270349","url":null,"abstract":"Dimensionality reduction or feature extraction has been widely used in applications that require a set of data to be represented by a small set of variables. A linear projection is often chosen due to its computational attractiveness. The calculation of the linear basis that best explains the data is usually addressed using the Karhunen-Loeve transform (KLT). Moreover, for applications where real-time performance and flexibility to accommodate new data are required, the linear projection is implemented in FPGAs due to their fine-grain parallelism and reconfigurability properties. Currently, the optimization of such a design in terms of area usage is considered as a separate problem to the basis calculation. In this paper, we propose a novel approach that couples the calculation of the linear projection basis and the area optimization problems under a probabilistic Bayesian framework. The power of the proposed framework is based on the flexibility to insert information regarding the implementation requirements of the linear basis by assigning a proper prior distribution. Results using real-life examples demonstrate the effectiveness of our approach","PeriodicalId":354940,"journal":{"name":"2006 IEEE International Conference on Field Programmable Technology","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129777482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Optimal temporal partitioning based on slowdown and retiming 基于减速和重定时的最优时间分区

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270344

Christian Plessl, M. Platzner, L. Thiele

引用次数: 2

Reconfigurable FLUX networks 可重构FLUX网络

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270298

S. Vassiliadis, I. Sourdis

引用次数: 5

Hardalign: a parallel pairwise alignment hardware application 硬对齐:一个并行的成对对齐硬件应用程序

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270350

G. Moritz, H. S. Lopes, C. R. E. Lima

引用次数: 0

Combining hardware reconfiguration and adaptive computation for a novel SoC design methodology 结合硬件重构与自适应计算的SoC设计方法

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270331

V. Rana, M. Santambrogio, S. Memik, D. Sciuto

引用次数: 3

Customizable FPGA-based architecture for video applications in real time 可定制的基于fpga的架构，用于实时视频应用

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270353

G. Saldaña-González, M. Arias-Estrada

引用次数: 2

FPGA implementation of a fuzzy controller for automobile DC-DC converters 汽车DC-DC变换器模糊控制器的FPGA实现

2006 IEEE International Conference on Field Programmable Technology Pub Date : 2006-12-01 DOI: 10.1109/FPT.2006.270317

J. Álvarez, A. Lago, A. Nogueiras, C. Martinez-Peñalver, J. Marcos, J. Doval‐Gandoy, Ó. López

引用次数: 14