Optimal temporal partitioning based on slowdown and retiming

Abstract

This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit's performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. A mixed integer linear program (MILP) formulation of the problem was provided, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. The application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture was presented