Hardalign: a parallel pairwise alignment hardware application

Abstract

This paper describes the design and implementation of a hardware for parallel pairwise alignment, implemented in a FPGA device. This system is aimed at aligning pairs of proteins, using a dynamic programming algorithm. The alignment is done in parallel thanks to a pipelined approach. All functional blocks are described in detail. Experiments to evaluate the performance of the system were done for pairs of proteins with up to 2000 amino acids-long. Hardalign was compared with a similar algorithm implemented in software and running in a PC, resulting in a 1:5 speed-up ratio