A C compiler for implementing FPGA based bit-serial DSP systems

Abstract

This paper describes the implementation and application of a compiler used to generate FPGA based bit-serial DSP system designs using a subset of the C programming language. To exploit the relative low hardware cost of bit-serial operations, the compiler employs techniques developed for conventional optimizing compilers, namely predicated static single assignment transformations and predicated speculation, to extract fine-grained parallelism from high-level algorithms. The compiler targets a synthesizable VHDL bit-serial library, relying on a conventional VHDL backend toolchain for placement and routing