FPGA acceleration of the tate pairing in characteristic 2

Robert Ronan, Colm O'hEigeartaigh, Colin C. Murphy, M. Scott, T. Kerins
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引用次数: 23

Abstract

This paper presents a dedicated hardware implementation of the cryptographic Tate pairing on an elliptic curve of characteristic 2 using theetaT method. Efficient techniques for pairing computation are discussed and optimised hardware architectures are presented. A hardware pipelining scheme is described, which provides a dramatic reduction in pairing computation time. A cryptographic processor for computation of the bilinear pairing is presented and implemented on an FPGA. It is demonstrated that an FPGA forms an ideal basis for pairing processor implementation due to ease of reconfigurability and the opportunity for rapid prototyping. Implementation results are provided for pairing calculation on an FPGA over the base field
特性2中状态对的FPGA加速
本文提出了一种用etat方法在特征为2的椭圆曲线上实现密码Tate配对的专用硬件实现。讨论了有效的配对计算技术,并给出了优化的硬件架构。描述了一种硬件流水线方案,该方案大大减少了配对计算时间。提出了一种用于双线性对计算的密码处理器,并在FPGA上实现。结果表明,由于易于重新配置和快速原型的机会,FPGA形成了配对处理器实现的理想基础。提供了基于基场的FPGA上的配对计算的实现结果
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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