1994 Proceedings. 44th Electronic Components and Technology Conference最新文献_第5页

A method for the optimization of a CMOS driven, center tap terminated (CTT) network in a shared bus design 一种在共享总线设计中优化CMOS驱动、中心抽头端接(CTT)网络的方法

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/ECTC.1994.367598

F.J. Cericola, B. K. Bhattacharyya

引用次数: 4

Fine line thin dielectric circuit board characterization 细线薄介质线路板表征

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/ECTC.1994.367537

C. S. Chang, A. Agrawal

引用次数: 11

Solder joint reliability of surface mount chip resistors/capacitors on insulated metal substrates 绝缘金属基板上表面贴装片式电阻/电容的焊点可靠性

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/ECTC.1994.367551

J. Suhling, R.W. Johnson, J. White, K.W. Matthai, R. Knight, C. S. Romanczuk, S.W. Burcham

{"title":"Solder joint reliability of surface mount chip resistors/capacitors on insulated metal substrates","authors":"J. Suhling, R.W. Johnson, J. White, K.W. Matthai, R. Knight, C. S. Romanczuk, S.W. Burcham","doi":"10.1109/ECTC.1994.367551","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367551","url":null,"abstract":"For enhanced heat transfer, insulated metal substrates are attractive alternatives to the FR-4 printed circuit boards which have been conventionally used in automotive engine controllers. Although appealing from the viewpoint of enhanced thermal performance, the high coefficient of thermal expansion of aluminum relative that of FR-4 boards leads to a increased probability of fatigue failures of surface mount solder connections subjected to thermal cycling. In this work, the thermal fatigue life and reliability of solder joints used to attach components to insulated metal substrates has been studied using finite element modeling and actual life testing. In particular, this investigation has examined the reliability of solder connections for ceramic chip resistors and chip capacitors. Several two-dimensional (plane stress and plane strain) and three-dimensional nonlinear finite element models have been prepared and executed for both chip resistors and chip capacitors on insulated metal substrates. Several common sizes of the resistors/capacitors have been modeled including 1206, 0805, 0603, and 0402. Attributes of the finite element models included elastic-plastic solder constitutive behavior, large deformations, and thermal cycling. Initiation of solder joint fatigue cracking was estimated using the predicted plastic strains within a Coffin-Manson type fatigue model. The fatigue life predictions of the finite element analyses have been correlated with solder joint crack initiation and life measurements for actual components under thermal cycling. A broad matrix of test configurations with various substrate materials, resistor/capacitor sizes, and encapsulants has been considered.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121188887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Manufacturing stresses in die due to die attach process 由于模具附着过程造成的模具制造应力

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/ECTC.1994.367623

P. Tsao, Arkady S. Voloshin

{"title":"Manufacturing stresses in die due to die attach process","authors":"P. Tsao, Arkady S. Voloshin","doi":"10.1109/ECTC.1994.367623","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367623","url":null,"abstract":"Manufacturing of the electronic packages consisting of different materials leads to the development of the residual stresses due to mismatch in the coefficients of thermal expansion. Thus, to properly assess service life of the packages, those stresses must be taken into account. An experimental technique, the digital image analysis enhanced moire interferometry ( DIAEMI), was used to measure the in-situ out-of-plane displacements of the die due to the die-attach process. This information was related to the residual stresses in the die. Several test dies, with and without coating, were prepared and two different bonding materials, \"low-stress\" and \"high-stress\", were used for analysis of the induced stresses. The initial and final (after die-attach) surface contour patterns of the dies were observed and recorded. Out-of-plane displacements of the dies were obtained and induced stresses were calculated by a hybrid finite element method. The results show that stresses in die induced by high-stress bonding material are on average five times higher than the stresses induced by low-stress material. It was also found that during die-attach some of residual stresses induced by chip's coating were released. The obtained results were compared with the straight forward finite element method prediction. It shows that the stresses predicted by the straight forward finite element analysis are much higher than the stresses obtained by the hybrid method.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121569197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Development of a high performance TQFP package 高性能TQFP封装的开发

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/ECTC.1994.367651

P. Hoffman, D. Liang, D. Mahulikar, A. Parthasarathi

引用次数: 6

Concurrent packaging architecture design 并行封装架构设计

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/ECTC.1994.367648

L. Cao, J. Krusius

引用次数: 10

A method of designing a group of bumps for C4 packages to maximize the number of bumps and minimize the number of package layers 一种为C4包装设计一组凸点的方法，使凸点数量最大化，包装层数最少

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/ECTC.1994.367595

N. Gasparini, B. Bhattacharyya

引用次数: 13

Epoxy encapsulation on Ceramic Quad Flat Packs 环氧树脂封装陶瓷四平面包装

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/ECTC.1994.367617

T. Carden, J. Clementi, S. Engle

{"title":"Epoxy encapsulation on Ceramic Quad Flat Packs","authors":"T. Carden, J. Clementi, S. Engle","doi":"10.1109/ECTC.1994.367617","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367617","url":null,"abstract":"The Ceramic Quad Flat Pack (CQFP) is a high performance, low cost technology for surface mount applications. It is an extension of the Metallized Ceramic (MC) and Metallized Ceramic with Polyimide (MCP) product base. These finished modules conform to JEDEC I/O and footprint standards. The packages are available in 0.5 mm and 0.4 mm lead pitches with flexibility to address unique application requirements such as body sizes or lead counts/pitches. Semiconductor die interconnection is performed using either flip chip (C4-Controlled Collapse Chip Connection) attach or wirebonding. Excellent package reliability with no intrinsic wear out failure mechanism results by encapsulating solder joints from the silicon C4 die and peripheral lead to ceramic carrier. IBM evaluated several encapsulant configurations, and tested over 2000 encapsulated carriers and 897000 individual solder joints during development and qualification. Epoxy encapsulation of solder joint connections on CQFP's has been successfully implemented in production across several IBM manufacturing sites. This enhancement eliminates any intrinsic failure mechanism associated with fatigue wear out. It is a significant extension of a low cost and high reliability product technology.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127064636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Rationalization of gold ball bond shear strengths 金球粘结剂抗剪强度的合理化

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/ECTC.1994.367588

R. Pantaleón, J. Sánchez-Mendoza, M. Mena

引用次数: 6

The effect of the cross-section of outlead on lead skew 引线截面对引线偏斜的影响

1994 Proceedings. 44th Electronic Components and Technology Conference Pub Date : 1994-05-01 DOI: 10.1109/ECTC.1994.367544

T. Momose, H. Yagi, S. Kawano, T. Ikenaga, Y. Nishikubo

引用次数: 0