2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)最新文献_第4页

Compact 200V Diode Constructed on Thick SOI Wafer 在厚SOI晶圆上构造的紧凑的200V二极管

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147711

J. Pjencak, Ladislav Seliga

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A Systematic Characterization Method for Time-resolved Stability and Reliability Issues on Lateral GaN Power Devices 横向GaN功率器件时间解决稳定性和可靠性问题的系统表征方法

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147699

Yifei Huang, Q. Jiang, Sen Huang, Xinyu Liu

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Novel Diode Structure for Ultra-Law-Loss RC-IGBTs 超律损耗rc - igbt新型二极管结构

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147707

Y. Yamashita, S. Machida, J. Saito, Masaru Senoo

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Stability Analysis of Parallel SiC power MOSFETs based on a Virtual Prototype 基于虚拟样机的并联SiC功率mosfet稳定性分析

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147660

Michel Nagel, Ivana Kovacevic-Badstuebner, Race Salvatore, D. Popescu, B. Popescu, D. Romano, Giulio Antonini, U. Grossner

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Mechanism of Threshold Voltage Instability in SiC MOSFETs and Impacts on Dynamic Switching SiC mosfet阈值电压不稳定机理及其对动态开关的影响

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147608

Junsong Jiang, Mohan Tian, Wen Ji, Zhihao Hu, Haoran Li, Yuzheng Guo, Zhaofu Zhang, Xi Tang, Cungang Hu, Wenping Cao

{"title":"Mechanism of Threshold Voltage Instability in SiC MOSFETs and Impacts on Dynamic Switching","authors":"Junsong Jiang, Mohan Tian, Wen Ji, Zhihao Hu, Haoran Li, Yuzheng Guo, Zhaofu Zhang, Xi Tang, Cungang Hu, Wenping Cao","doi":"10.1109/ISPSD57135.2023.10147608","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147608","url":null,"abstract":"The threshold voltage ($V_{text{TH}}$) instability of silicon carbon (SiC) metal-oxide semiconductor field-effect transistors (MOSFETs) are investigated by pulsed bias characterizations. The $V_{text{TH}}$ instability is observed at a time range from nanoseconds (ns) to seconds. The bias induced $V_{text{TH}}$ shift caused by is observed within 40 ns. It is also found that a negative gate bias induces a negative $V_{text{TH}}$ shift while a positive gate bias induces a positive $V_{text{TH}}$ shift. The carrier trapping and de-trapping processes into the gate oxide cause the $V_{text{TH}}$ instabilities and they are explained by the energy band diagrams. The TCAD simulations are performed to demonstrate the exsistence of the electric fields to sweep carriers into the trapping region under both positive and negative gate bias conditions. The capacitance-voltage characterizations and first-principles calculations are further carried out to evaluate the defect distribution and explore the intrinsic source of high-density interface traps near the SiC-SiO2 interface.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115928591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Mechanism Analysis and Improved Model for HCI in 200V STI-based Triple RESURF LDMOS With n-p-n Layer 200V si基n-p-n层三层重熔LDMOS HCI机理分析及改进模型

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147414

Zuquan Zheng, M. Qiao, Wenliang Liu, Xingrui Long, Penglong Xu, Chunxia Ma, Feng Lin, Bo Zhang

引用次数: 0

A SEB Hardened Trench Gate DMOS with HfO2 Gate Dielectric and Decelerating Electric Field Layer in Parasitic NPN Base 一种具有HfO2栅极介质和减速电场层的寄生NPN基SEB硬化沟栅DMOS

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147721

Jian Fang, Yibo Lei, Zhou Fang, Lijuan Shi, Lingli Tang, Xihe Yang, Ling Yan, Bo Zhang

{"title":"A SEB Hardened Trench Gate DMOS with HfO2 Gate Dielectric and Decelerating Electric Field Layer in Parasitic NPN Base","authors":"Jian Fang, Yibo Lei, Zhou Fang, Lijuan Shi, Lingli Tang, Xihe Yang, Ling Yan, Bo Zhang","doi":"10.1109/ISPSD57135.2023.10147721","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147721","url":null,"abstract":"The paper proposes a single-event burnout (SEB) hardened trench-gate DMOS with HfO2 gate dielectric and a decelerating electric field layer in the parasitic NPN. The proposed device presents remarkable potential to tolerate SEB. High-$k$ gate dielectric (HfO2) is adopted to obtain a higher channel doping concentration while maintaining the normal $V_{text{TH}}$, thereby suppressing the secondary breakdown of parasitic NPN. The decelerating electric field layer will reduce the $beta$ of parasitic NPN. For the hardened trench gate DMOS with breakdown voltage of 572V under irradiation linear energy transfer value of 1pC/µm (96MeV/mg/cm2), numerical results (without considering the self-heating effect) show that the SEB threshold voltage is 554V, while the conventional device's is 132V. The SEB threshold voltage is increased by 32%. When the LET value is smaller than 0.6pC/µm, the SEB threshold voltage is over 570V. The SEB threshold voltage of proposed device almost equals its original breakdown voltage. It is meaningful for SEB hardening design of power devices.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126895453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Improvement of HCI and HTRB Reliability on 100V pLDMOS for 48V Battery Applications 用于48V电池的100V pLDMOS HCI和HTRB可靠性的改进

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147539

Dong-Hoon Park, Min-Woo Kim, Jun-Ki Min, Kwang-Young Ko, Sang-Gi Lee

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5 A/1.17 kV NiO/$beta$-Ga2O3 heterojunction power rectifier with high-temperature operation capability up to 548 K 5 A/1.17 kV NiO/$beta$-Ga2O3异质结功率整流器，高温工作能力高达548 K

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147400

Zhengpeng Wang, H. Gong, Xinxin Yu, F. Ren, S. Gu, Youdou Zheng, Rong Zhang, Jiandong Ye

{"title":"5 A/1.17 kV NiO/$beta$-Ga2O3 heterojunction power rectifier with high-temperature operation capability up to 548 K","authors":"Zhengpeng Wang, H. Gong, Xinxin Yu, F. Ren, S. Gu, Youdou Zheng, Rong Zhang, Jiandong Ye","doi":"10.1109/ISPSD57135.2023.10147400","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147400","url":null,"abstract":"Industrial power devices are required to conduct at least several amperes current in the on-state while blocking at least hundreds of volts in the off-state. In this work, high-temperature operational $text{NiO}/beta-text{Ga}_{2}mathrm{O}_{3}$ vertical p-n heterojunction diodes (HJDs) with ampere-level forward current and kV -level reverse breakdown voltage $(V_{b})$ have been demonstrated. The temperature-dependent current-voltage characteristics reveal that trap-assisted tunneling (TAT) current dominates the forward conduction mechanism of HJDs, while the leakage current is dominated by variable range hopping (VRH) mechanism under the high reverse bias. The resultant large-area (1×1 mm2) HJD rectifiers exhibit a superior forward on-state current of 5 A, a nearly-unity ideality factor and a large $V_{b}$ of 1.17 kV operated at a high temperature up to 548 K. The low deterioration rate of forward on-state current (1.24 mA/K at 4 V) and $V_{b}$ (0.95 V/K) with temperature implies high reliability of HJD, evidencing the promising potential of Ga2O3-based power diodes in harsh-environment power systems.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127179534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low Loss Lateral Insulated Gate Bipolar Transistor with an Anode PNP Structure and Integrated Freewheeling Diode 具有阳极PNP结构和集成自由转二极管的低损耗侧绝缘栅双极晶体管

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI: 10.1109/ISPSD57135.2023.10147701

Yuxi Wei, Jie Wei, Pengcheng Zhu, Kemeng Yang, Kaiwei Dai, Jie Li, Junnan Wang, Bo Zhang, X. Luo

{"title":"Low Loss Lateral Insulated Gate Bipolar Transistor with an Anode PNP Structure and Integrated Freewheeling Diode","authors":"Yuxi Wei, Jie Wei, Pengcheng Zhu, Kemeng Yang, Kaiwei Dai, Jie Li, Junnan Wang, Bo Zhang, X. Luo","doi":"10.1109/ISPSD57135.2023.10147701","DOIUrl":"https://doi.org/10.1109/ISPSD57135.2023.10147701","url":null,"abstract":"A low loss lateral insulated gate bipolar transistor (LIGBT) features an anode PNP structure and an integrated freewheeling diode (iFWD), named as PD LIGBT, is proposed and investigated by simulation. For the anode PNP structure, its P+ Collector shorts to the potential extracting contact above the P-top layer of iFWD, and its emitter is the anode of the LIGBT. During turning off period with the increasing $V_{text{AK}}$, the PNP is activated and hole current is allowed to flow through the PNP to iFWD. It suppresses the hole injection of the anode into the N-drift region, and thus the current density decreases quickly. Therefore, the PD LIGBT achieves a fast turning-off speed and reduces the $E_{text{off}}$ significantly. In the on-state with low anode voltage $V_{text{AK}}$, the PNP is not activated, hence the PD LIGBT gets into bipolar conduction without snapback effect. Moreover, the iFWD can realize reverse conduction and obtain a low reverse recovery charge ($Q_{text{rr}}$). Compared with the SSA and STA LIGBTs, the proposed LIGBT reduces the $E_{text{off}}$ by 81% and 70% at the same on-state voltage drop ($V_{text{on}}$), respectively. The reverse recovery charge of the proposed device is reduced by 49.5% compared with that of SSA LIGBT.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126411086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0