A SEB Hardened Trench Gate DMOS with HfO2 Gate Dielectric and Decelerating Electric Field Layer in Parasitic NPN Base

Abstract

The paper proposes a single-event burnout (SEB) hardened trench-gate DMOS with HfO2 gate dielectric and a decelerating electric field layer in the parasitic NPN. The proposed device presents remarkable potential to tolerate SEB. High-$k$ gate dielectric (HfO2) is adopted to obtain a higher channel doping concentration while maintaining the normal $V_{\text{TH}}$, thereby suppressing the secondary breakdown of parasitic NPN. The decelerating electric field layer will reduce the $\beta$ of parasitic NPN. For the hardened trench gate DMOS with breakdown voltage of 572V under irradiation linear energy transfer value of 1pC/µm (96MeV/mg/cm2), numerical results (without considering the self-heating effect) show that the SEB threshold voltage is 554V, while the conventional device's is 132V. The SEB threshold voltage is increased by 32%. When the LET value is smaller than 0.6pC/µm, the SEB threshold voltage is over 570V. The SEB threshold voltage of proposed device almost equals its original breakdown voltage. It is meaningful for SEB hardening design of power devices.