Mechanism Analysis and Improved Model for HCI in 200V STI-based Triple RESURF LDMOS With n-p-n Layer

Abstract

This paper researches the hot carrier injection (HCI) degradation of 200V STI-based triple reduced surface field (RESURF) lateral double-diffused MOSFET (LDMOS). The degradation phenomenon of specific on-resistance ($R_{\text{on},\text{sp}}$) increasing, then decreasing and finally increasing at low gate voltage ($V_{\text{gs}}$) was discovered in HCI test. First electron injection, then hole injection, and finally interface state generation, three mechanisms were put forward to account for this degradation phenomenon. With the assistance of TCAD tools, it can be concluded that the degradation of $R_{\text{on},\text{sp}}$ caused by both electron traps and hole traps is much greater at STI corner than elsewhere for the same amount. Furthermore, an improved model based on above three mechanisms is proposed. This model introduces a parameter $\alpha(V_{\text{gs}})$ to characterize the influence of impact ionization peak locations on degradation.