用于48V电池的100V pLDMOS HCI和HTRB可靠性的改进

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI:10.1109/ISPSD57135.2023.10147539

Dong-Hoon Park, Min-Woo Kim, Jun-Ki Min, Kwang-Young Ko, Sang-Gi Lee

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引用次数: 0

摘要

本文研究了100V PLDMOS器件在HCI应力作用下栅极氧化物击穿和BVdss游走的改善。在之前的研究中，在60V或更低的电压下应用多场极板扩展，可以改善100V PLDMOS的HCI栅氧化物击穿。然而，由于改变多场板的电场分布，使BVdss在加应力后发生了walk-in。通过TCAD仿真证实了电势和冲击电离的变化，并通过改变金属场板和n型下沉设计，以及改变多场板，实现了100V PLDMOS器件的HCI和HTRB的改善。基于这些结果，我们提出了一种新的100V级PLDMOS结构。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Improvement of HCI and HTRB Reliability on 100V pLDMOS for 48V Battery Applications

In this paper, improvement of gate oxide breakdown and BVdss walk-in after HCI stress of 100V PLDMOS devices was studied. The poly field plate extension applied at 60V or lower in the previous study could improve gate oxide breakdown by HCI of 100V PLDMOS. However, BVdss walk-in occurred after on-stress due to a change in the electric field distribution by changing the poly field plate. Changes in electrical potential and impact ionization were confirmed through TCAD simulation and improvements in HCI and HTRB of 100V PLDMOS devices were achieved by changing the metal field plates and N-type sinker design, in addition to poly field plates. Based on these results, we propose a novel structure for 100V class PLDMOS.

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2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)

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