The Fourth International Workshop on Junction Technology, 2004. IWJT '04.最新文献_第2页

The simulation breakdown characteristic of 4H-SiC SBD with edge termination extension 边端延伸的4H-SiC SBD击穿特性仿真

The Fourth International Workshop on Junction Technology, 2004. IWJT '04. Pub Date : 2004-03-15 DOI: 10.1109/IWJT.2004.1306789

Hongliang Lv, Yimen Zhang, Yu-Ming Zhang

引用次数: 1

Study of Co silicidation process for 0.18/0.15/spl mu/m CMOS technology 0.18/0.15/spl μ m CMOS工艺的Co硅化工艺研究

The Fourth International Workshop on Junction Technology, 2004. IWJT '04. Pub Date : 2004-03-15 DOI: 10.1109/IWJT.2004.1306780

Hu Hengsheng, Chen Shoumian

引用次数: 0

Dopant redistribution induced by Ni silicidation at 300/spl deg/C 300℃/spl温度下镍硅化引起的杂质重分布

The Fourth International Workshop on Junction Technology, 2004. IWJT '04. Pub Date : 2004-03-15 DOI: 10.1109/IWJT.2004.1306778

Yu-Long Jiang, A. Agarwal, G. Ru, X. Qu, Bingzong Li

引用次数: 4

The thermal stability of zirconium aluminate high-k film on strained SiGe layer 铝酸锆高k薄膜在应变SiGe层上的热稳定性

The Fourth International Workshop on Junction Technology, 2004. IWJT '04. Pub Date : 2004-03-15 DOI: 10.1109/IWJT.2004.1306857

Z. Di, Miao Zhang, Weili Liu, S. Luo, Z. An, Zhengxuan Zhang, Zhitang Song, Chenglu Lin

引用次数: 0

The nanoelectronic CMOS era: silicon meets the other materials on the roadmap 纳米电子CMOS时代:硅与路线图上的其他材料相遇

The Fourth International Workshop on Junction Technology, 2004. IWJT '04. Pub Date : 2004-03-15 DOI: 10.1109/IWJT.2004.1306744

S. Deleonibus

{"title":"The nanoelectronic CMOS era: silicon meets the other materials on the roadmap","authors":"S. Deleonibus","doi":"10.1109/IWJT.2004.1306744","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306744","url":null,"abstract":"Historically, innovations have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50 nm gate length CMOS devices. We point out the main issues to address in order to investigate and push the limits of CMOS technology. The alternative architectures allowing to increase devices drivability and reduce power are reviewed. Among the materials options to be integrated, HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. New architectures and options are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials, Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. Functionality of devices in the range of 5 nm channel length has been demonstrated showing that CMOS technology could still be used in the future if we manage to implement new materials and device architecture options.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114730805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Novel NiSi technology utilizing Ti/Ni/TiN structure and fluorine implantation for thermal stability improvement by suppression of abnormal oxidation 新型NiSi技术利用Ti/Ni/TiN结构和氟注入抑制异常氧化来提高热稳定性

The Fourth International Workshop on Junction Technology, 2004. IWJT '04. Pub Date : 2004-03-15 DOI: 10.1109/IWJT.2004.1306776

J. Yun, Soon-Young Oh, H. Ji, Bin-Feng Huang, Y. Park, Jin-Suk Wang, H. Lee

引用次数: 1

Effect of rapid thermal annealing on Ti/Al-GaN contacts 快速热退火对Ti/Al-GaN接触的影响

The Fourth International Workshop on Junction Technology, 2004. IWJT '04. Pub Date : 2004-03-15 DOI: 10.1109/IWJT.2004.1306787

Xue Li, Yong Kang, Xiangyang Li, H. Gong, Haxiong Fang

{"title":"Effect of rapid thermal annealing on Ti/Al-GaN contacts","authors":"Xue Li, Yong Kang, Xiangyang Li, H. Gong, Haxiong Fang","doi":"10.1109/IWJT.2004.1306787","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306787","url":null,"abstract":"Non-intentionally-doped wurtzite GaN epitaxial layers used in this study were grown on (0001) sapphire by metal organic chemical vapour deposition technique. Ti/Al(24nm/90nm) contacts were deposited by ion beam sputtering. Effect of rapid thermal annealing on Ti/Al-GaN contacts was investigated by I-V measurements and AES depth profiles. Surface morphologies were characterized by AFM. Schottky barrier height and specific contact resistivity decreased at first and then increased as annealing temperature increased. The lowest specific contact resistivity was obtained at 600/spl deg/C, i.e.3.04 /spl times/ 10/sup -4//spl Omega//spl middot/cm/sup 2/. However, the ideality factors increased with increase of annealing temperatures. Auger depth profile analysis showed that Ti had diffused into annealed GaN samples, a heavily n-doped layer formed at Ti/GaN interface. The tunneling current mechanism played a role in increase of ideality factors after annealing. The changes of surface morphologies at different annealing temperatures were characterized by AFM. The root mean square roughness of the as-grown sample was 2.9/spl Aring/. After 600/spl deg/C annealing, the root mean square roughness increased to 41.5/spl Aring/. These results showed that thermal annealing-induced changes near the surface region of contacts were significant. The thermal stability of contacts needs further study. Ohmic contacts formed at 600/spl deg/C are due to lower barrier height and tunneling current transport.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130747002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

InGaP/InGaAs dual-channel transistor InGaP/InGaAs双通道晶体管

The Fourth International Workshop on Junction Technology, 2004. IWJT '04. Pub Date : 2004-03-15 DOI: 10.1109/IWJT.2004.1306790

H. Chuang, C. Uang, S. Cheng, Chun-Yuan Chen, P. Lai, C. Kao, Y. Tsai, W. Hsu, Wen-Chau Liu

引用次数: 0

The collapse of gate electrode in high-current implanter of batch type 间歇式大电流植入器栅电极的坍塌

The Fourth International Workshop on Junction Technology, 2004. IWJT '04. Pub Date : 2004-03-15 DOI: 10.1109/IWJT.2004.1306753

Y. Kawasaki, K. Tokunaga, K. Horita, K. Mitsuda, A. Yamaguchi, A. Ueno, A. Teratani, T. Katayama, K. Hayami, A. Togawa, Y. Ohno, M. Yoneda

引用次数: 6

Numerical simulation of hot-carrier degradation in SOI MOSFETs SOI mosfet热载流子退化的数值模拟

The Fourth International Workshop on Junction Technology, 2004. IWJT '04. Pub Date : 2004-03-15 DOI: 10.1109/IWJT.2004.1306855

Qing Lin, M. Zhu, Yan-jun Wu, Xinyun Xie, Zhengxuan Zhang, Cheng-lu Lin

引用次数: 1