{"title":"0.18/0.15/spl μ m CMOS工艺的Co硅化工艺研究","authors":"Hu Hengsheng, Chen Shoumian","doi":"10.1109/IWJT.2004.1306780","DOIUrl":null,"url":null,"abstract":"In this paper, two approaches to form CoSi/sub 2/, Co/Ti and Co/TiN, were studied. It was found that reactive Ti was helpful to reduce the influence of surface condition with non-uniform monosilicide formation even without surface cleaning. However, Co/TiN without surface cleaning could not form monosilicide at all. When the thermal budget of RTP2 is too high, the disilicide on Boron doped polylines was easier to be degraded, both poor Rsh distribution and rougher surface were seen. Based on stable R/sub sh/ and junction leakage performance of patterned wafers, it can be said that the Co salicide process is successfully being developed for 0.18/spl mu/m technology, and has the capability to be extended to at least 0.15/spl mu/m technology.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Study of Co silicidation process for 0.18/0.15/spl mu/m CMOS technology\",\"authors\":\"Hu Hengsheng, Chen Shoumian\",\"doi\":\"10.1109/IWJT.2004.1306780\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, two approaches to form CoSi/sub 2/, Co/Ti and Co/TiN, were studied. It was found that reactive Ti was helpful to reduce the influence of surface condition with non-uniform monosilicide formation even without surface cleaning. However, Co/TiN without surface cleaning could not form monosilicide at all. When the thermal budget of RTP2 is too high, the disilicide on Boron doped polylines was easier to be degraded, both poor Rsh distribution and rougher surface were seen. Based on stable R/sub sh/ and junction leakage performance of patterned wafers, it can be said that the Co salicide process is successfully being developed for 0.18/spl mu/m technology, and has the capability to be extended to at least 0.15/spl mu/m technology.\",\"PeriodicalId\":342825,\"journal\":{\"name\":\"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-03-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWJT.2004.1306780\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWJT.2004.1306780","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Study of Co silicidation process for 0.18/0.15/spl mu/m CMOS technology
In this paper, two approaches to form CoSi/sub 2/, Co/Ti and Co/TiN, were studied. It was found that reactive Ti was helpful to reduce the influence of surface condition with non-uniform monosilicide formation even without surface cleaning. However, Co/TiN without surface cleaning could not form monosilicide at all. When the thermal budget of RTP2 is too high, the disilicide on Boron doped polylines was easier to be degraded, both poor Rsh distribution and rougher surface were seen. Based on stable R/sub sh/ and junction leakage performance of patterned wafers, it can be said that the Co salicide process is successfully being developed for 0.18/spl mu/m technology, and has the capability to be extended to at least 0.15/spl mu/m technology.
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