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A 1.25 Gb/s fully integrated optical receiver for SI-POF applications 1.25 Gb/s全集成光接收器，用于SI-POF应用
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662273
C. Gimeno, C. Sánchez-Azqueta, S. Celma, C. Aldea, C. Cahill
{"title":"A 1.25 Gb/s fully integrated optical receiver for SI-POF applications","authors":"C. Gimeno, C. Sánchez-Azqueta, S. Celma, C. Aldea, C. Cahill","doi":"10.1109/ECCTD.2013.6662273","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662273","url":null,"abstract":"This paper presents the design of a 1.25 Gb/s fully integrated BiCMOS optical receiver for short reach applications through low-cost step index plastic optical fiber. The limited bandwidth caused by the fiber is compensated by a continuous-time equalizer. A low noise transimpedance amplifier with some peaking overcomes the limitation introduced by the integrated photodiode. A post-amplifier has been included to generate the required digital output levels. The design achieves 1.25 Gb/s through 50 m SI-POF with a power consumption of 148 mW and a sensitivity of -16.4 dBm for a BER of 10-12. Simulation results are provided.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130717367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An estimation method for the 3 port S-parameters with 1 port measurements 一种基于1个端口测量的3个端口s参数估计方法
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662246
N. Maeda, S. Fukui, T. Sekine, Yasuhiro Takahashi
{"title":"An estimation method for the 3 port S-parameters with 1 port measurements","authors":"N. Maeda, S. Fukui, T. Sekine, Yasuhiro Takahashi","doi":"10.1109/ECCTD.2013.6662246","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662246","url":null,"abstract":"An estimation method of the three-port S-parameters for reciprocal circuits is presented. In this method, several known loads are connected to two of the ports and reflection characteristic of the remaining port is measured. Therefore, there is no need to connect network analyzer to the ports which are connected to the known loads. S-parameters are obtained by solving a linear system equations and quadratic equations only. In addition, a method for determining the port voltages from the estimated S parameters is also described, Then applying this method to estimate the S-parameters of an immunity test system, validness of this method has been confirmed. The proposed method will be applied when there is no common ground between each ports.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133270978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Filter-induced bifurcation in simple spiking circuits 简单尖峰电路中的滤波器诱导分岔
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662339
Shota Kirikawa, Toshimichi Saito
{"title":"Filter-induced bifurcation in simple spiking circuits","authors":"Shota Kirikawa, Toshimichi Saito","doi":"10.1109/ECCTD.2013.6662339","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662339","url":null,"abstract":"This paper studies filter-induced bifurcation phenomena in simple spiking circuits. Repeating integrate-and-fire dynamics between a periodic base signal and a threshold, the circuit outputs spike-trains. The dynamics depends crucially on the shape of the base signal and we make the base signal by filtering a square source signal. As a key parameter of the filter varies, the shape of the base signal varies and the model can exhibit bifurcation phenomena of various periodic/chaotic spiketrains. Effects of the ideal low-pass filter is considered. Presenting a simple test circuit, typical phenomena are also confirmed experimentally.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114324485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implementation of a pulse-holding Time-to-Digital Converter on an FPGA 在FPGA上实现脉冲保持时间-数字转换器
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662271
F. Brandonisio, Alberto Prodomo, Michael Peter Kennedy, E. Napoli
{"title":"Implementation of a pulse-holding Time-to-Digital Converter on an FPGA","authors":"F. Brandonisio, Alberto Prodomo, Michael Peter Kennedy, E. Napoli","doi":"10.1109/ECCTD.2013.6662271","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662271","url":null,"abstract":"In this work, we describe the implementation of a pulse-holding Time-to-Digital Converter (TDC) on a Xilinx Spartan 6 FPGA. We describe the operation of a pulse-holding TDC and we compare it with that of a pulse-shrinking TDC, which is the most similar TDC in the literature. We then illustrate a Simulink model of a pulse-holding TDC and the TDC that was implemented on a FPGA. The pulse-holding TDC uses a moving average filter to remove the quantization noise and improve the precision of the measurements. We show from simulations and experiments that the maximum modulus of the difference between the the input and output of the TDC can be reduced from 2 ns to less than 70 ps by means of a moving average filter.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114333647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Jointly optimal high-order error feedback and realization for roundoff noise minimization in 2-D state-space digital filters 联合优化二维状态空间数字滤波器的高阶误差反馈与舍入噪声最小化实现
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662277
T. Hinamoto, A. Doi, Wu-Sheng Lu
{"title":"Jointly optimal high-order error feedback and realization for roundoff noise minimization in 2-D state-space digital filters","authors":"T. Hinamoto, A. Doi, Wu-Sheng Lu","doi":"10.1109/ECCTD.2013.6662277","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662277","url":null,"abstract":"The joint optimization problem of high-order error feedback and realization for minimizing roundoff noise at filter output subject to l2-scaling constraints is investigated for two-dimensional (2-D) state-space digital filters. Linear algebraic techniques that convert the problem at hand into an unconstrained optimization problem are explored, and an efficient quasi-Newton algorithm is then applied to solve the unconstrained optimization problem iteratively. In this connection, closed-form formulas are derived for fast and accurate gradient evaluation. Finally a numerical example is presented to illustrate the validity and effectiveness of the proposed algorithm.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123487783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Frequency noise of CMOS LC tank oscillators operating in weak inversion 弱反转时CMOS LC槽振荡器的频率噪声
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662207
J. Anders, M. Ortmanns
{"title":"Frequency noise of CMOS LC tank oscillators operating in weak inversion","authors":"J. Anders, M. Ortmanns","doi":"10.1109/ECCTD.2013.6662207","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662207","url":null,"abstract":"In this paper, we present an analytical model for a CMOS LC tank oscillator with its active devices operating in weak inversion. Our model combines nonlinear, stochastic circuit analysis in the form of the so-called stochastic averaging method proposed by Stratonovich with advanced MOS device modeling in the form of the EKV-model. The presented approach not only provides - for the first time - simple, yet accurate closed-form expressions for the oscillation frequency and amplitude of a CMOS LC tank oscillator operating in weak inversion but also allows us to derive closed-form expressions for the phase and frequency noise of the oscillator originating from both the parasitic resistance of the tank coil and the white noise generated in the cross-coupled MOS transistor pair. Thanks to their relatively compact and closed form, the presented results can not only be used for circuit optimization during the initial design phase but also convey important insights into the dependency of phase noise on design parameters such as the transconductance of the active devices.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123029891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An analog dynamic memory array for neuromorphic hardware 一种用于神经形态硬件的模拟动态存储器阵列
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662229
Matthias Hock, Andreas Hartel, J. Schemmel, K. Meier
{"title":"An analog dynamic memory array for neuromorphic hardware","authors":"Matthias Hock, Andreas Hartel, J. Schemmel, K. Meier","doi":"10.1109/ECCTD.2013.6662229","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662229","url":null,"abstract":"We describe an array of capacitor based cells capable of storing analog voltages and currents for highly configurable large-scale neuromorphic hardware. A novel refresh scheme based on content-addressable memory as well as a slow and simple voltage ramp generator is presented. The circuits have been simulated in a 65nm mixed-signal low power process. Key characteristics are an area consumption of 175 μm2 and a power consumption of less than 125nW per stored value. A prototype chip has been designed and submitted for fabrication.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128527677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Implementation trade-offs of the density matrix renormalization group algorithm on kilo-processor architectures 密度矩阵重整化群算法在千处理器架构上的实现权衡
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662251
C. Nemes, Gergely Barcza, Z. Nagy, O. Legeza, P. Szolgay
{"title":"Implementation trade-offs of the density matrix renormalization group algorithm on kilo-processor architectures","authors":"C. Nemes, Gergely Barcza, Z. Nagy, O. Legeza, P. Szolgay","doi":"10.1109/ECCTD.2013.6662251","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662251","url":null,"abstract":"Numerical analysis of strongly correlated quantum lattice models has a great importance in quantum physics. The exponentially growing size of the Hilbert space makes these computations difficult, however sophisticated algorithms have been developed to balance the size of the effective Hilbert space and the accuracy of the simulation. One of these methods is the density matrix renormalization group (DMRG) algorithm which has become the leading numerical tool in the study of low dimensional lattice problems of current interest. In the algorithm a high computational problem can be translated to a list of dense matrix operations, which makes it an ideal application to fully utilize the computing power residing in both current multi-core processors and novel kilo-processor architectures.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130857354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A compact low-voltage first-order temperature-compensated CMOS current reference 一种紧凑的低压一阶温度补偿CMOS电流基准
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662219
B. Calvo, C. Azcona, N. Medrano-Marqués, S. Celma, M. D. R. V. Bernal
{"title":"A compact low-voltage first-order temperature-compensated CMOS current reference","authors":"B. Calvo, C. Azcona, N. Medrano-Marqués, S. Celma, M. D. R. V. Bernal","doi":"10.1109/ECCTD.2013.6662219","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662219","url":null,"abstract":"This paper presents the design of two new low-voltage first-order temperature compensated CMOS current references. To achieve compact topologies able to operate under low voltage with low power consumption, they are based on the simplest approach of cross-coupled current mirrors, and compensation is obtained by introducing a temperature dependent current mirror ratio. Results for 0.18 μm CMOS implementations show that the proposed 1 μA references operate with supplies down to 1 V showing temperature drifts below 238 ppm/°C over the (-40 to 120°C) range, which makes them suitable for low-cost portable applications.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121244439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Extended constraint management for analog and mixed-signal IC design 模拟和混合信号IC设计的扩展约束管理
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662319
Andreas Krinke, M. Mittag, Göran Jerke, J. Lienig
{"title":"Extended constraint management for analog and mixed-signal IC design","authors":"Andreas Krinke, M. Mittag, Göran Jerke, J. Lienig","doi":"10.1109/ECCTD.2013.6662319","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662319","url":null,"abstract":"The consideration of a growing number of design constraints is becoming a bottleneck in the design of analog and mixed-signal integrated circuits and is blocking more, much-needed automation in this area. In this paper, we propose a solution to these issues with a new methodology for constraint propagation and transformation. This technique allows designers and software tools to consider all relevant constraints when modifying a design, regardless of where these constraints were originally created. We integrated our ideas in an industrial design flow. The implementation of an electrical constraint type demonstrates the practical relevance. With constraints of this type the ON resistance of power stages in smart power ICs can be limited for the first time.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127157044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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