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2013 European Conference on Circuit Theory and Design (ECCTD)最新文献

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Low power secure CSSAL bit-parallel multiplier over GF(24) in 0.18μm CMOS technology 基于0.18μm CMOS技术的GF(24)低功耗安全csal位并行乘法器
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662327
Câncio Monteiro, Yasuhiro Takahashi, T. Sekine
{"title":"Low power secure CSSAL bit-parallel multiplier over GF(24) in 0.18μm CMOS technology","authors":"Câncio Monteiro, Yasuhiro Takahashi, T. Sekine","doi":"10.1109/ECCTD.2013.6662327","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662327","url":null,"abstract":"In this paper, we present the post layout simulation result of our previously proposed charge-sharing symmetric adiabatic logic (CSSAL) in comparison with the symmetric adiabatic logic, 2N-2N2P, and the TDPL in the bit-parallel cellular multiplier over GF(24). The transitional supply current and the power fluctuation of each logic style are compared in order to verify the logic ability for resistance against side-channel analysis attacks in cryptographic hardware implementation. The full custom layout is designed in cadence virtuoso IC6.1 with the chip size of 172×155 μm2, and the cyclical power consumption of 14 pJ at 12.5 MHz using 0.18 μm CMOS technology for the CSSAL multiplier has achieved, while TDPL has 183 × 173 μm2 of the chip size, and the power consumption is 122.6 pJ which is about nine times higher than the one of the CSSAL. The low-power adiabatic logics are also thoroughly investigated, and the comparative data demonstrate that the proposed CSSAL multiplier has similar performance on power reduction and resistive to thwart side channel analysis at low frequency application.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126902670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A configurable IC to contol, readout, and calibrate an array of biosensors 一种可配置的集成电路，用于控制、读出和校准一系列生物传感器
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662331
S. Ghoreishizadeh, S. Carrara, G. Micheli
{"title":"A configurable IC to contol, readout, and calibrate an array of biosensors","authors":"S. Ghoreishizadeh, S. Carrara, G. Micheli","doi":"10.1109/ECCTD.2013.6662331","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662331","url":null,"abstract":"We present a novel integrated circuit for a biosensing data acquisition chain. The circuit controls and reads out five bimolecular sensors as well as pH and temperature sensors for biosensor calibration. The IC supports both chronoamper-ometry (CA) and cyclic voltammetry (CV) measurements, which are commonly used in biosensing. Different voltage waveforms are generated to control CV by using a single configurable waveform generator and programmable constant voltage levels are produced to enable CA. To reduce the area and power consumption of the interface electronics, a unified circuit is designed for CV, CA and pH readout. The biosensors produce currents that are converted by a 13.5-bit sigma delta analog to digital converter. The circuit has been designed and realized in 0.18 μW technology. It consumes 711 μW from a 1.8 V supply voltage, making it suitable for remotely powered and implantable applications.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129284912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Emulation of analog memristors using low yield digital switching memristors 用低产量数字开关忆阻器仿真模拟忆阻器
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662250
Á. Rák, G. Cserey
{"title":"Emulation of analog memristors using low yield digital switching memristors","authors":"Á. Rák, G. Cserey","doi":"10.1109/ECCTD.2013.6662250","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662250","url":null,"abstract":"In this paper, we propose circuits for emulating analog purpose memristors (APM) purely composed from digital switching memristors or digital purpose memristors (DPM). Our design is also robust against memristor defects therefore this can be applied even in low yield technology where defects occur at high probability. Our simulations show that the switching noise of the circuits decreases with the number of memristors and the production yield of the circuit is no lower than the production yield of the digital switching memristors.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121455858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel electronics for high-speed FM-AFM in life science applications 高速FM-AFM在生命科学中的应用
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662241
Benedikt Schlecker, M. Ortmanns, J. Anders, G. Fantner
{"title":"Novel electronics for high-speed FM-AFM in life science applications","authors":"Benedikt Schlecker, M. Ortmanns, J. Anders, G. Fantner","doi":"10.1109/ECCTD.2013.6662241","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662241","url":null,"abstract":"In this paper we present a novel system architecture for high-speed FM-AFM electronics. The proposed system consists of a PLL-based FM demodulator preceded by a SSB modulator and driving electronics ensuring a stable self-oscillation of the cantilever. Thanks to the SSB upconverion preceding the FM-demodulator, the system allows for demodulation bandwidths as large as the cantilever resonance frequency, opening up the way to real-time FM-AFM of biological processes. Electrical measurements of a PCB-based prototype verify the proposed architecture.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124482684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
NERO mastering 300k CNN cells NERO掌握了30万个CNN细胞
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662202
R. Braunschweig, Jens Müller, Jan Müller, R. Tetzlaff
{"title":"NERO mastering 300k CNN cells","authors":"R. Braunschweig, Jens Müller, Jan Müller, R. Tetzlaff","doi":"10.1109/ECCTD.2013.6662202","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662202","url":null,"abstract":"A novel massively-parallel fine-grain architecture featuring a digital emulation of Cellular Nonlinear Networks (CNN) is presented. A virtual cellular network is processed line-by-line by a locally connected linear array of processing elements. The resulting computing system is able to execute complex CNN program code consisting of consecutive operations. Furthermore we present a scalable FPGA implementation of this architecture for currently up to 480 × 640 cells with a precision up to 18 bit.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125664799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Networks, multipoles and multiports 网络，多极和多端口
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662191
A. Reibiger
{"title":"Networks, multipoles and multiports","authors":"A. Reibiger","doi":"10.1109/ECCTD.2013.6662191","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662191","url":null,"abstract":"Starting point is the definition of networks as ordered pairs of a skeleton and a constitutive relation. The skeleton describes the topological structure of a network. The constitutive relation describes the physical properties assigned to its branch set. The behavior of a network is defined as the set of all signal pairs obeying its constitutive relation and both Kirchhoff's laws. Multipoles are introduced as ordered pairs consisting of a network and a family of terminal classes. The terminal classes are disjoint subsets of the node set of the corresponding network. Multiports are defined as multipoles whose terminal classes contain exactly two nodes. Based on these concepts a general theory of the terminal behavior of multipoles is developed.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"466 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121949725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A wideband lumped-element model for arbitrarily shaped integrated inductors 任意形状集成电感器的宽带集总元模型
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662233
Faabio Passos, M. Fino, E. Roca
{"title":"A wideband lumped-element model for arbitrarily shaped integrated inductors","authors":"Faabio Passos, M. Fino, E. Roca","doi":"10.1109/ECCTD.2013.6662233","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662233","url":null,"abstract":"In this paper a model based on lumped elements is used to characterize integrated inductors. The method proposed allows the modelling of integrated inductors for a wide range of frequencies, thus granting the overall characterization of the device and the evaluation of important design parameters such as inductance, quality factor and resonance frequency. The model can easily be applied to any polygonal shape inductor due to its inductance calculation through self and mutual inductances. Electromagnetic simulations results are presented to demonstrate the validation of the model.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115843329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A novel output transformer based highly linear RF-DAC architecture 一种基于高线性RF-DAC结构的新型输出变压器
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662314
E. Bechthum, G. Radulov, J. Briaire, G. Geelen, A. Roermund
{"title":"A novel output transformer based highly linear RF-DAC architecture","authors":"E. Bechthum, G. Radulov, J. Briaire, G. Geelen, A. Roermund","doi":"10.1109/ECCTD.2013.6662314","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662314","url":null,"abstract":"A major limitation of the linearity of Current Steering (CS) RF-DACs is the large output voltage swing (typically 1Vpp), which couples to sensitive internal nodes and thereby causes non-linear distortion. This paper proposes a novel approach for the linearization of the CS RF-DAC. An output transformer decouples the output from the circuit core and attenuates the voltage swing seen by the RF-DAC current cells. A lumped element model of a transformer is used in calculations and simulations to analyze the performance of the transformer in the Mixing-DAC application, and to select optimal design parameters for high linearity. Verification with a simulation model of an RF-DAC shows that the output related non-linearity (IMD3) of the CS RF-DAC improves with about 14dB when the proposed transformer parameters are used.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134181601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Realizable reduction of interconnect models with dense coupling 具有密集耦合的互连模型的可实现化简
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662294
Pekka Miettinen, M. Honkala, M. Valtonen, J. Roos
{"title":"Realizable reduction of interconnect models with dense coupling","authors":"Pekka Miettinen, M. Honkala, M. Valtonen, J. Roos","doi":"10.1109/ECCTD.2013.6662294","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662294","url":null,"abstract":"This paper describes a model-order reduction (MOR) method to reduce an interconnect circuit with possibly dense inductive and capacitive coupling. The method uses partitioning to divide the original circuit into small parts that can be then approximated accurately with low-order reduced-order models (ROMs). The use of low-order ROMs enables the use of positive-valued macromodels with standard RLCK realization. The coupling is reduced with a two-stage reduction separately for the inductive and capacitive coupling. This allows for efficient sparsification of the coupling effect. The method is verified with test simulations of the 65-nm technology node and is shown to produce good reduction results in terms of CPU speedup and generated error.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125213700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Trigger-wave propagation in arbitrary metrics in asynchronous cellular logic arrays 异步蜂窝逻辑阵列中任意度量的触发波传播
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662312
P. Mroszczyk, P. Dudek
{"title":"Trigger-wave propagation in arbitrary metrics in asynchronous cellular logic arrays","authors":"P. Mroszczyk, P. Dudek","doi":"10.1109/ECCTD.2013.6662312","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662312","url":null,"abstract":"This paper presents the idea of an asynchronous cellular pixel-parallel logic array for global image processing tasks using trigger-wave propagation in a medium with a hardware-controlled metric. The principles of wave propagation in cellular four-connected logic arrays emulating different distance measure norms are explained and verified using a simplified switched RC circuit model. The proposed gate array consists of only 13 transistors per pixel and was implemented in a standard 90 nm CMOS technology. It provides the propagation medium applicable for binary image skeletonization, Voronoi tessellation or distance transformation tasks where calculating distances in a particular metric (e. g. Euclidean, Manhattan, Chessboard, etc.) is desired.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"415 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117298952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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