Low power secure CSSAL bit-parallel multiplier over GF(24) in 0.18μm CMOS technology

Abstract

In this paper, we present the post layout simulation result of our previously proposed charge-sharing symmetric adiabatic logic (CSSAL) in comparison with the symmetric adiabatic logic, 2N-2N2P, and the TDPL in the bit-parallel cellular multiplier over GF(24). The transitional supply current and the power fluctuation of each logic style are compared in order to verify the logic ability for resistance against side-channel analysis attacks in cryptographic hardware implementation. The full custom layout is designed in cadence virtuoso IC6.1 with the chip size of 172×155 μm2, and the cyclical power consumption of 14 pJ at 12.5 MHz using 0.18 μm CMOS technology for the CSSAL multiplier has achieved, while TDPL has 183 × 173 μm2 of the chip size, and the power consumption is 122.6 pJ which is about nine times higher than the one of the CSSAL. The low-power adiabatic logics are also thoroughly investigated, and the comparative data demonstrate that the proposed CSSAL multiplier has similar performance on power reduction and resistive to thwart side channel analysis at low frequency application.