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2013 European Conference on Circuit Theory and Design (ECCTD)最新文献

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A parallelized distance transformation architecture for FPGAs fpga的并行距离变换结构
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662222
M. Atay, M. Yalçin
{"title":"A parallelized distance transformation architecture for FPGAs","authors":"M. Atay, M. Yalçin","doi":"10.1109/ECCTD.2013.6662222","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662222","url":null,"abstract":"Object detection, object recognition, shape matching and path planning are important tasks in computer vision systems. Distance transformation is an algorithm commonly utilized in such systems. In this paper, a new FPGA based distance transform implementation is proposed to be used in object recognition and shape matching systems. The proposed method is designed to meet high performance, low power and low area requirements. The Xilinx Spartan-6 FPGA is preferred for the implementation.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115003799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Memristor macromodel and its application to neuronal spike generation 忆阻器宏观模型及其在神经元脉冲产生中的应用
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662306
Sangho Shin, Kyungmin Kim, S. Kang
{"title":"Memristor macromodel and its application to neuronal spike generation","authors":"Sangho Shin, Kyungmin Kim, S. Kang","doi":"10.1109/ECCTD.2013.6662306","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662306","url":null,"abstract":"This paper introduces a memristor-based neuronal spike event generator, in which the memristor models the nonlinear behavior of opening and closing of sodium and potassium ion channels. The neuronal action potential describing both the integrate-and-fire spiking events and the refractory period of nerve membrane cells is enabled by utilizing dual time-constants offered by the bistable resistance state of practical memristive devices. A memristor macromodel which is capable of representing both the threshold effects and boundary assurance is also presented.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121312479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Pulse Width Modulation using a recently developed CMOS core circuit 利用最新开发的 CMOS 核心电路进行脉冲宽度调制
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662201
I. C. Göknar, S. Minaei, M. Yildiz, Ergul Akcakaya
{"title":"Pulse Width Modulation using a recently developed CMOS core circuit","authors":"I. C. Göknar, S. Minaei, M. Yildiz, Ergul Akcakaya","doi":"10.1109/ECCTD.2013.6662201","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662201","url":null,"abstract":"In this paper a new approach for a Pulse Width Modulation (PWM) circuit operating in current-mode using a CMOS classifier core circuit, and its application to level crossing are presented. The proposed architecture is much simpler than existing PWM methods and the generated PWM signal can be controlled electronically through the control currents of a core circuit. Measurements performed with DU-TCC 1209*, an IC designed and manufactured using 0.35 μm AMS technology parameters, show a perfect match with theoretical results.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127464640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Fractional derivative constrained design of FIR filter with prescribed magnitude and phase responses 具有规定幅度和相位响应的FIR滤波器的分数阶导数约束设计
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662298
C. Tseng, Su-Ling Lee
{"title":"Fractional derivative constrained design of FIR filter with prescribed magnitude and phase responses","authors":"C. Tseng, Su-Ling Lee","doi":"10.1109/ECCTD.2013.6662298","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662298","url":null,"abstract":"In this paper, the designs of fractional derivative constrained FIR filters with prescribed magnitude and phase responses are presented. First, the definition of fractional derivative is reviewed. Then, FIR filters with complex-valued frequency responses are designed by minimizing the integral squares error under the constraint that the actual response and ideal response have several same fractional derivatives at the prescribed frequency point. Finally, the designs of low group delay low-pass filter and Hilbert transformer are demonstrated to show the effectiveness of the proposed design method.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"782 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123282064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A low power analog RAM implementation for in-probe beamforming in ultrasound imaging 超声成像探头内波束形成的低功耗模拟RAM实现
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662297
Surya Sharma, T. Ytterdal
{"title":"A low power analog RAM implementation for in-probe beamforming in ultrasound imaging","authors":"Surya Sharma, T. Ytterdal","doi":"10.1109/ECCTD.2013.6662297","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662297","url":null,"abstract":"An Analog RAM architecture for beamforming based on switched current circuits is presented. The proposed architecture allows the sharing of the same bias current for different memory cells, hence results in a large amount of power saving. The beamformer consists of total 16 channels and in each channel a delay line with depth of 16 has been implemented. The input frequency is 10MHz and a sampling frequency of 25MHz is used. The proposed architecture achieves 50dB of dynamic range and 49dB of SNDR with power dissipation of 760μW for one channel. The ARAM is implemented in 180nm CMOS technology and occupies 250×150μm2 per channel.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125313050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Focused calibration for advanced RF test with embedded RF detectors 集中校准先进的射频测试与嵌入式射频探测器
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662259
Quoc-Tai Duong, J. Dabrowski
{"title":"Focused calibration for advanced RF test with embedded RF detectors","authors":"Quoc-Tai Duong, J. Dabrowski","doi":"10.1109/ECCTD.2013.6662259","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662259","url":null,"abstract":"In this paper a technique suitable for on-chip IP3/IP2 RF test by embedded RF detectors is presented. A lack of spectral selectivity of the detectors and diverse nonlinearity of the circuit under test (CUT) impose stiff constraints on the respective test measurements for which focused calibration approach and a support by customized models of CUT is necessary. Also cancellation of second-order intermodulation effects produced by the detectors under the two-tone test is required. The test technique is introduced using a polynomial model of the CUT. Simulation example of a practical CMOS LNA under IP3/IP2 RF test with embedded RF detectors is presented showing a good measurement accuracy.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"349 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116554153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 176×120 pixel CMOS vision chip for Gaussian filtering with massivelly Parallel CDS and A/D-conversion 一种176×120像素CMOS视觉芯片，用于高斯滤波，具有大规模并行CDS和A/ d转换
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662293
Manuel Suárez-Cambre, V. Brea, D. Cabello, J. Fernández-Berni, R. Carmona-Galán, Á. Rodríguez-Vázquez
{"title":"A 176×120 pixel CMOS vision chip for Gaussian filtering with massivelly Parallel CDS and A/D-conversion","authors":"Manuel Suárez-Cambre, V. Brea, D. Cabello, J. Fernández-Berni, R. Carmona-Galán, Á. Rodríguez-Vázquez","doi":"10.1109/ECCTD.2013.6662293","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662293","url":null,"abstract":"This paper conveys a proof-of-concept chip for Gaussian pyramid generation for image feature detectors. Gaussian filtering and image resizing are performed with a switched-capacitor (SC) network. The chip is conceived as the mapping of a CMOS-3D architecture for feature detectors onto a conventional technology, with some functionality removed, and the corresponding area overhead with respect to that of a CMOS-3D architecture, but preserving masivelly parallel Correlated Double Sampling (CDS) and A/D conversion. The chip has been fabricated on a die of 5×5 mm2 with 0.18 μm CMOS technology, achieving an array of 176×120 sensing elements (pixels). The pixels are arranged in Processing Elements (PEs). Every PE comprises four photodiodes, four SC nodes, one CDS circuit, and local circuitry for one ADC. Every PE occupies an area of 44×44 μm2. The chip senses an image and computes the Gaussian pyramid with an average power consumption lower than 75 nW/pixel at 30 frames/s.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122584906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Mixed-mode simulations to check stability of an adaptive constant on-time DC-DC converter 混合模式仿真以检验自适应恒定导通时间DC-DC变换器的稳定性
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662270
F. Bizzarri, A. Brambilla, S. Saggini, G. S. Gajani
{"title":"Mixed-mode simulations to check stability of an adaptive constant on-time DC-DC converter","authors":"F. Bizzarri, A. Brambilla, S. Saggini, G. S. Gajani","doi":"10.1109/ECCTD.2013.6662270","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662270","url":null,"abstract":"In this paper we consider performances of a version of a constant on-time (COT) DC/DC converter. There is a renewed interest in COT converters since they offer interesting features such as speed and low cost implementation. The duty cycle of these converters is varied by acting on the working frequency and this introduces problems in modeling, in deriving transfer functions and in studying stability properties. Largely adopted averaging methods, that assume that the control loop bandwidth is much smaller than the converter switching frequency, risk to be no longer applicable since COT converters do not satisfy this hypothesis. Also conventional methods and techniques that exploit Floquet theory and variational model can not be applied since differential algebraic equations modeling switching converters show discontinuities in the vector field (switching). In this paper we use saltation matrices to allow the application of consolidated numerical techniques to the specific case of COT converters and, more in general, to the broad class of switching converters modeled by mixed analog/digital models.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128451611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analysis of myoelectric signals using a Field Programmable SoC 使用现场可编程SoC分析肌电信号
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662255
B. Borbely, Zoltán Kincses, Zsolt Vörösházi, Z. Nagy, P. Szolgay
{"title":"Analysis of myoelectric signals using a Field Programmable SoC","authors":"B. Borbely, Zoltán Kincses, Zsolt Vörösházi, Z. Nagy, P. Szolgay","doi":"10.1109/ECCTD.2013.6662255","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662255","url":null,"abstract":"A platform design for the analysis of human myoelectric signals (MES) is presented. Offline recorded multichannel signals of forearm muscles are processed with a Field Programmable SoC in order to classify different movement patterns to control human-assisting electromechanical systems with multiple degrees of freedom (e.g. a prosthetic hand). Benchmark results of an ANSI C implementation are shown to assess the raw performance of the built-in ARM cores of the SoC. Possible computational bottlenecks are located based on the results and custom hardware implementations are shown to fully utilize the flexibility and performance of the used hardware platform.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129459442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
State space analysis of mixed signal systems with switched feedback and delay 具有切换反馈和延迟的混合信号系统的状态空间分析
2013 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2013-11-14 DOI: 10.1109/ECCTD.2013.6662195
C. Zorn, T. Thiessen, Timon Brückner, M. Ortmanns, W. Mathis
{"title":"State space analysis of mixed signal systems with switched feedback and delay","authors":"C. Zorn, T. Thiessen, Timon Brückner, M. Ortmanns, W. Mathis","doi":"10.1109/ECCTD.2013.6662195","DOIUrl":"https://doi.org/10.1109/ECCTD.2013.6662195","url":null,"abstract":"This paper discusses how switching delay or respectively excess loop delay affects the dynamics of sampled systems with discrete control. It is presented how a switched system model enables an analytical description of the maximum states in dependency of the input amplitude, the system coefficients and delay. Furthermore, this paper provides an analytical method to scale the maximum states to a specific value in order to reduce the increased dynamics caused by the delay.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129647628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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