{"title":"Trigger-wave propagation in arbitrary metrics in asynchronous cellular logic arrays","authors":"P. Mroszczyk, P. Dudek","doi":"10.1109/ECCTD.2013.6662312","DOIUrl":null,"url":null,"abstract":"This paper presents the idea of an asynchronous cellular pixel-parallel logic array for global image processing tasks using trigger-wave propagation in a medium with a hardware-controlled metric. The principles of wave propagation in cellular four-connected logic arrays emulating different distance measure norms are explained and verified using a simplified switched RC circuit model. The proposed gate array consists of only 13 transistors per pixel and was implemented in a standard 90 nm CMOS technology. It provides the propagation medium applicable for binary image skeletonization, Voronoi tessellation or distance transformation tasks where calculating distances in a particular metric (e. g. Euclidean, Manhattan, Chessboard, etc.) is desired.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"415 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 European Conference on Circuit Theory and Design (ECCTD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCTD.2013.6662312","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper presents the idea of an asynchronous cellular pixel-parallel logic array for global image processing tasks using trigger-wave propagation in a medium with a hardware-controlled metric. The principles of wave propagation in cellular four-connected logic arrays emulating different distance measure norms are explained and verified using a simplified switched RC circuit model. The proposed gate array consists of only 13 transistors per pixel and was implemented in a standard 90 nm CMOS technology. It provides the propagation medium applicable for binary image skeletonization, Voronoi tessellation or distance transformation tasks where calculating distances in a particular metric (e. g. Euclidean, Manhattan, Chessboard, etc.) is desired.