{"title":"具有密集耦合的互连模型的可实现化简","authors":"Pekka Miettinen, M. Honkala, M. Valtonen, J. Roos","doi":"10.1109/ECCTD.2013.6662294","DOIUrl":null,"url":null,"abstract":"This paper describes a model-order reduction (MOR) method to reduce an interconnect circuit with possibly dense inductive and capacitive coupling. The method uses partitioning to divide the original circuit into small parts that can be then approximated accurately with low-order reduced-order models (ROMs). The use of low-order ROMs enables the use of positive-valued macromodels with standard RLCK realization. The coupling is reduced with a two-stage reduction separately for the inductive and capacitive coupling. This allows for efficient sparsification of the coupling effect. The method is verified with test simulations of the 65-nm technology node and is shown to produce good reduction results in terms of CPU speedup and generated error.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Realizable reduction of interconnect models with dense coupling\",\"authors\":\"Pekka Miettinen, M. Honkala, M. Valtonen, J. Roos\",\"doi\":\"10.1109/ECCTD.2013.6662294\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a model-order reduction (MOR) method to reduce an interconnect circuit with possibly dense inductive and capacitive coupling. The method uses partitioning to divide the original circuit into small parts that can be then approximated accurately with low-order reduced-order models (ROMs). The use of low-order ROMs enables the use of positive-valued macromodels with standard RLCK realization. The coupling is reduced with a two-stage reduction separately for the inductive and capacitive coupling. This allows for efficient sparsification of the coupling effect. The method is verified with test simulations of the 65-nm technology node and is shown to produce good reduction results in terms of CPU speedup and generated error.\",\"PeriodicalId\":342333,\"journal\":{\"name\":\"2013 European Conference on Circuit Theory and Design (ECCTD)\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-11-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 European Conference on Circuit Theory and Design (ECCTD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECCTD.2013.6662294\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 European Conference on Circuit Theory and Design (ECCTD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCTD.2013.6662294","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Realizable reduction of interconnect models with dense coupling
This paper describes a model-order reduction (MOR) method to reduce an interconnect circuit with possibly dense inductive and capacitive coupling. The method uses partitioning to divide the original circuit into small parts that can be then approximated accurately with low-order reduced-order models (ROMs). The use of low-order ROMs enables the use of positive-valued macromodels with standard RLCK realization. The coupling is reduced with a two-stage reduction separately for the inductive and capacitive coupling. This allows for efficient sparsification of the coupling effect. The method is verified with test simulations of the 65-nm technology node and is shown to produce good reduction results in terms of CPU speedup and generated error.