C. Gimeno, C. Sánchez-Azqueta, S. Celma, C. Aldea, C. Cahill
{"title":"A 1.25 Gb/s fully integrated optical receiver for SI-POF applications","authors":"C. Gimeno, C. Sánchez-Azqueta, S. Celma, C. Aldea, C. Cahill","doi":"10.1109/ECCTD.2013.6662273","DOIUrl":null,"url":null,"abstract":"This paper presents the design of a 1.25 Gb/s fully integrated BiCMOS optical receiver for short reach applications through low-cost step index plastic optical fiber. The limited bandwidth caused by the fiber is compensated by a continuous-time equalizer. A low noise transimpedance amplifier with some peaking overcomes the limitation introduced by the integrated photodiode. A post-amplifier has been included to generate the required digital output levels. The design achieves 1.25 Gb/s through 50 m SI-POF with a power consumption of 148 mW and a sensitivity of -16.4 dBm for a BER of 10-12. Simulation results are provided.","PeriodicalId":342333,"journal":{"name":"2013 European Conference on Circuit Theory and Design (ECCTD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 European Conference on Circuit Theory and Design (ECCTD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCTD.2013.6662273","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents the design of a 1.25 Gb/s fully integrated BiCMOS optical receiver for short reach applications through low-cost step index plastic optical fiber. The limited bandwidth caused by the fiber is compensated by a continuous-time equalizer. A low noise transimpedance amplifier with some peaking overcomes the limitation introduced by the integrated photodiode. A post-amplifier has been included to generate the required digital output levels. The design achieves 1.25 Gb/s through 50 m SI-POF with a power consumption of 148 mW and a sensitivity of -16.4 dBm for a BER of 10-12. Simulation results are provided.