Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference最新文献_第6页

Toward a formal semantics of IEEE Std. VHDL 1076 IEEE标准VHDL 1076的形式化语义研究

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI: 10.1109/EURDAC.1993.410687

S. Olcoz, J. Colom

引用次数: 31

GAFPGA: Genetic algorithm for FPGA technology mapping GAFPGA:用于FPGA技术映射的遗传算法

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI: 10.1109/EURDAC.1993.410654

V. Kommu, I. Pomeranz

引用次数: 26

Best-so-far vs. where-you-are: New perspectives on simulated annealing for CAD 到目前为止最好的vs.你在哪里:CAD模拟退火的新观点

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI: 10.1109/EURDAC.1993.410698

K. Boese, A. Kahng, C. Tsao

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引用次数: 6

DSP datapath synthesis eliminating global interconnect 消除全局互连的DSP数据路径合成

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI: 10.1109/EURDAC.1993.410615

A. A. Duncan, D. C. Hendry

引用次数: 9

Dynamic variable reordering for BDD minimization BDD最小化的动态变量重排序

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI: 10.1109/EURDAC.1993.410627

E. Felt, G. York, R. Brayton, A. Sangiovanni-Vincentelli

引用次数: 60

Analysis of multi-process VHDL specifications with a Petri net model 用Petri网模型分析多进程VHDL规范

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI: 10.1109/EURDAC.1993.410679

J. Muller, H. Kramer

引用次数: 11

The CALLAS synthesis system and its application to mechatronic ASIC design problems CALLAS综合系统及其在机电集成电路设计中的应用

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI: 10.1109/EURDAC.1993.410650

P. Windirsch, P. Duzy

引用次数: 0

A performance driven hierarchical partitioning placement algorithm 一种性能驱动的分层分区放置算法

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI: 10.1109/EURDAC.1993.410613

T. Gao, C. Liu, Kuang-Chien Chen

引用次数: 6

Concepts and methods for version modeling 版本建模的概念和方法

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI: 10.1109/EURDAC.1993.410658

M. Oussalah, Guilaine Talens, M. Colinas

引用次数: 8

Modeling of real bistables in VHDL 真实双表的VHDL建模

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI: 10.1109/EURDAC.1993.410677

A. Acosta, A. Barriga, M. Valencia-Barrero, M. J. Díaz, J. Huertas

引用次数: 5