一种性能驱动的分层分区放置算法

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI:10.1109/EURDAC.1993.410613

T. Gao, C. Liu, Kuang-Chien Chen

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引用次数: 6

摘要

提出了一种新的分层分区放置算法。目标函数表示为总导线长度和最大电路延迟的加权和。使用特殊的平衡规则来确保区域中组件数量之间的良好平衡。总导线长度和最大电路延迟在划分过程的每一步有效地估计和更新。实验结果非常鼓舞人心。

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A performance driven hierarchical partitioning placement algorithm

A new hierarchical partitioning placement algorithm is presented. The objective function is formulated as a weighted sum of the total wire length and the maximum circuit delay. Special balancing rules are used to assure a good balance between the numbers of components in the regions. Total wire length and maximum circuit delay are estimated and updated efficiently at each step of the partitioning process. Experimental results are very encouraging.<>

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来源期刊

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

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