{"title":"消除全局互连的DSP数据路径合成","authors":"A. A. Duncan, D. C. Hendry","doi":"10.1109/EURDAC.1993.410615","DOIUrl":null,"url":null,"abstract":"CASS (column architecture synthesis system) is a behavioral high level synthesis system for DSP applications. It uses a column based target architecture and in-the-cell routing to produce compact layout which eliminates the need for global wiring. This is achieved using bit-sliced cells which butt together to produce the data path. A description of the architecture and algorithms which produce the datapath is given. It is also shown that this approach gives large area savings when compared to a conventional system.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"DSP datapath synthesis eliminating global interconnect\",\"authors\":\"A. A. Duncan, D. C. Hendry\",\"doi\":\"10.1109/EURDAC.1993.410615\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"CASS (column architecture synthesis system) is a behavioral high level synthesis system for DSP applications. It uses a column based target architecture and in-the-cell routing to produce compact layout which eliminates the need for global wiring. This is achieved using bit-sliced cells which butt together to produce the data path. A description of the architecture and algorithms which produce the datapath is given. It is also shown that this approach gives large area savings when compared to a conventional system.<<ETX>>\",\"PeriodicalId\":339176,\"journal\":{\"name\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-09-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EURDAC.1993.410615\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1993.410615","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
DSP datapath synthesis eliminating global interconnect
CASS (column architecture synthesis system) is a behavioral high level synthesis system for DSP applications. It uses a column based target architecture and in-the-cell routing to produce compact layout which eliminates the need for global wiring. This is achieved using bit-sliced cells which butt together to produce the data path. A description of the architecture and algorithms which produce the datapath is given. It is also shown that this approach gives large area savings when compared to a conventional system.<>