Toward a formal semantics of IEEE Std. VHDL 1076

Abstract

The need for a formal interpretation of VHDL is addressed. The formal model used for this purpose is colored Petri nets because they can cover all aspects of VHDL. The authors start from the underlying executable model of VHDL based on communicating processes. The formal model of a VHDL description results from the specification in Petri net terms of the user-defined processes, the kernel process (VHDL simulator), and the communicating links between them. This approach can also be applied to other HDLs with the same underlying paradigm.<>