Analysis of multi-process VHDL specifications with a Petri net model

Abstract

A method for analyzing behavioral multiprocess VHDL specifications used for optimizing system-level synthesis is presented. To determine the access conflicts to the global data signals, the system behavior must be analyzed. Therefore the synchronization scheme is modeled as a Petri net, which can be minimized by transformation. A reduced case graph is regarded as a state transition graph of the system states. To calculate the probabilities of the access conflicts, the probability of observing the system in a certain state must be determined. This is done by calculation of the stationary distribution of a Markov chain.<>