TAU '02最新文献_第2页

A probabilistic approach to clock cycle prediction 时钟周期预测的概率方法

TAU '02 Pub Date : 2002-12-02 DOI: 10.1145/589411.589414

J. Dambre, D. Stroobandt, J. V. Campenhout

{"title":"A probabilistic approach to clock cycle prediction","authors":"J. Dambre, D. Stroobandt, J. V. Campenhout","doi":"10.1145/589411.589414","DOIUrl":"https://doi.org/10.1145/589411.589414","url":null,"abstract":"When developing new technologies, it is important to have an indication of the gain that can be achieved by exploring different research directions. Part of this gain is measured by achievable system performance. In this paper, we focus on the a priori prediction of clock speed as a measure for system performance.Previous approaches to clock cycle prediction were based on the summation of a number of (predicted) wire delays, equal to the maximum logic depth in a circuit. However, these methods do not consider the fact that the minimum clock cycle is determined by the largest combinatorial delay that occurs in a very complex and parallel interconnection topology. Indeed, in most circuits, there are a large number of paths with maximum or almost maximum logic depth. When implementing those circuits, any of these paths might become the path with maximal delay.In this paper, we present a new probabilistic model for predicting the maximal combinatorial path delay that partially captures the impact of the parallelism, present in real circuits. Our model is based on the distributions of the sum and of the maximum of a number of independent random variables. We experimentally validate our model using measured wire delay distributions.","PeriodicalId":338381,"journal":{"name":"TAU '02","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125809231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Timing analysis challenges for high speed CPUs at 90nm and below 90nm及以下高速cpu的时序分析挑战

TAU '02 Pub Date : 2002-12-02 DOI: 10.1145/589411.589420

A. Efrati, Moshe Kleyner

{"title":"Timing analysis challenges for high speed CPUs at 90nm and below","authors":"A. Efrati, Moshe Kleyner","doi":"10.1145/589411.589420","DOIUrl":"https://doi.org/10.1145/589411.589420","url":null,"abstract":"Advances of the VLSI technology into the sub-90nm processes, enabling complex CPU designs that work at GHz frequencies pose numerous design and verification challenges.In this invited presentation, we focus on challenges in timing analysis of CPUs working at GHz speeds and sub-90nm processes.We start by brief overview of Timing Analysis tool used for intel CPUs and the \"shell\" timing models used for large blocks and how they integrate into full-chip model. Hierarchical timing is emphasized as key enabler for handling full-chip timing.Next, short-term challenges are presented:Xtalk impact on timingActive interconnectMixed abstraction, device to full-chipUse of domino as characterized cells.An intermediate accuracy model for Xtalk is introduced, called SMCF, which adaptively adjust equivalent MCF of attackers based on slope relationship and an empiric formula.We go into some detail with an example of timing checks that need to be applied for domino cells, which are different from checks applied on static cells.Finally some mid-term challenges are described:Multiple Input SwitchingProcess and environment variabilitySleep transistors.As variability is covered in more depth in other papers at this conference we mention it briefly but bring some examples of MIS and sleep transistor issues.","PeriodicalId":338381,"journal":{"name":"TAU '02","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126976221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Explicit computation of performance as a function of process variation 显式计算性能作为过程变化的函数

TAU '02 Pub Date : 2002-12-02 DOI: 10.1145/589411.589413

L. Scheffer

引用次数: 32

Aggressive crunching of extracted RC netlists 对提取的RC网表进行积极的处理

TAU '02 Pub Date : 2002-12-02 DOI: 10.1145/589411.589426

V. Rao, J. Soreff, Ravichander Ledalla, Fred L. Yang

引用次数: 3

Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses GHz+总线中非开关受累者最坏情况串扰噪声的测定

TAU '02 Pub Date : 2002-12-02 DOI: 10.1145/589411.589430

Jun Chen, Lei He

引用次数: 4

Efficient algorithms for debugging timing constraint violations 用于调试违反时序约束的有效算法

TAU '02 Pub Date : 2002-12-02 DOI: 10.1145/589411.589423

Ali Dasdan

{"title":"Efficient algorithms for debugging timing constraint violations","authors":"Ali Dasdan","doi":"10.1145/589411.589423","DOIUrl":"https://doi.org/10.1145/589411.589423","url":null,"abstract":"A system of binary linear constraints or difference constraints (SDC) consists of a set of variables that are constrained by a set of unary or binary linear inequalities. In such diverse applications as scheduling, interface timing verification, real-time systems, multimedia systems, layout compaction, and constraint satisfaction, SDCs have successfully been used to model systems of both temporal and spatial constraints. Formally, an SDC is modeled by a weighted, directed graph called a constraint graph. The consistency (or feasibility) of an SDC means that there is at least one instantiation (or solution) of its variables that satisfies all its constraints. It is well known that the absence of positive cycles in a constraint graph implies the consistency of the corresponding SDC, so the consistency can be decided in strongly polynomial time. If the system is consistent, a solution can also be found in strongly polynomial time. However, if the system is inconsistent, there is no solution unless the system is repaired (or debugged). The debugging task is equivalent to freeing the corresponding constraint graph from all its positive cycles. All the previous algorithms for this task take time proportional to the number of positive cycles in the graph, which can grow exponentially. We have recently proposed a provably strongly polynomial-time algorithm for this task, i.e., an algorithm whose time complexity is polynomial in the size of the input constraint graph. In this paper, we propose extensions of this algorithm for different debugging scenarios. We theoretically and experimentally justify the efficiency and efficacy of our algorithms.","PeriodicalId":338381,"journal":{"name":"TAU '02","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125893853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Efficient switching window computation for cross-talk noise 串扰噪声的高效开关窗计算

TAU '02 Pub Date : 2002-12-02 DOI: 10.1145/589411.589429

Bhavana Thudi, D. Blaauw

{"title":"Efficient switching window computation for cross-talk noise","authors":"Bhavana Thudi, D. Blaauw","doi":"10.1145/589411.589429","DOIUrl":"https://doi.org/10.1145/589411.589429","url":null,"abstract":"In this paper, we present an efficient method for computing switching windows in the presence of delay noise. In static timing analysis, delay noise has traditionally been modeled using a simple switch-factor based noise model and the computation of switching windows is performed using an iterative algorithm where timing window propagation and switch factor updates are computed repeatedly until convergence. It was shown that the worst-case number of iterations required for convergence is O(n), where n is the number of gates in the circuit, resulting in an overall run time of O(n2). It was also shown that the iterations converge to different solutions, depending on the initial assumptions, making it unclear which solution is correct. In this paper, we show that the iterative nature of the problem is due to the switching-factor noise model and the order in which events are evaluated. Based on superposition model, we propose a time-sort based algorithm to compute the impact of delay noise on timing windows. We prove that the proposed algorithm has a run time that is linear with the circuit size. Since the algorithm is non-iterative and does not require initial assumptions, it eliminates the multiple solution problem. We tested the algorithm on a number of designs and show that it achieves significant speedup over the iterative approach.","PeriodicalId":338381,"journal":{"name":"TAU '02","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127839049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

From blind certainty to informed uncertainty 从盲目的确定到知情的不确定

TAU '02 Pub Date : 2002-12-02 DOI: 10.1145/589411.589419

K. Keutzer, M. Orshansky

引用次数: 24

Worst case clock skew under power supply variations 最坏的情况下，时钟偏差在电源变化

TAU '02 Pub Date : 2002-12-02 DOI: 10.1145/589411.589416

Min Zhao, Kaushik Gala, V. Zolotov, Yuhong Fu, R. Panda, R. Ramkumar, B. K. Agrawal

引用次数: 17

Clock schedule verification with crosstalk 时钟时间表验证与串音

TAU '02 Pub Date : 2002-12-02 DOI: 10.1145/589411.589428

H. Zhou

引用次数: 5