TAU '02最新文献

{"title":"Statistical timing analysis using bounds and selective enumeration","authors":"A. Agarwal, D. Blaauw, V. Zolotov, S. Vrudhula","doi":"10.1145/589411.589417","DOIUrl":"https://doi.org/10.1145/589411.589417","url":null,"abstract":"The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to the dependencies created by reconverging paths in the circuit. In this paper, we propose a new approach to statistical timing analysis which uses statistical bounds and selective enumeration to refine these bounds. First, we provide a formal definition of the statistical delay of a circuit and derive a statistical timing analysis method from this definition. Since this method for finding the exact statistical delay has exponential run time complexity with circuit size, we also propose a new method for computing statistical bounds which has linear run time complexity. We prove the correctness of the proposed bounds. Since we provide both a lower and upper bound on the true statistical delay, we can determine the quality of the bounds. If the computed bounds are not sufficiently close to each other, we propose the use of a heuristic to iteratively improve the bounds using selective enumeration of the sample space with additional run time. The proposed methods were implemented and tested on benchmark circuits. The results demonstrate that the proposed bounds have only a small error, which could be further reduced using selective enumeration with modest additional run time.","PeriodicalId":338381,"journal":{"name":"TAU '02","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128224413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Test structures for delay variability","authors":"D. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, S. Nassif, C. McDowell, A. Gattiker, Frank Liu","doi":"10.1145/589411.589435","DOIUrl":"https://doi.org/10.1145/589411.589435","url":null,"abstract":"With continued technology scaling, yield loss due to timing variation is becoming a significant concern. In particular, random and systematic process variation in devices and interconnect results in variable delay and operating speed along different logic and signal paths; these variations can erode timing windows and ultimately contribute to circuit failure. In this work, a test structure methodology is developed to support the evaluation of process variation and its impact on circuit speed.A newly designed variation test chip enables relatively simple measurement and evaluation of timing variation resulting from process and layout-induced variation. First, the fundamental test structure is a nine-stage ring oscillator (RO); a frequency-divided readout of the RO frequency serves as a clearly defined measure of circuit speed. A large family of ring oscillator test structures has been designed, where each structure is made sensitive to a particular device or interconnect variation source. Front-end-of-line (FEOL) or device variation sensitive structures enable examination of channel length variation as a function of different layout practices, including gate length (finger width), spacing between multiple fingers, orientation (vertical or horizontal), and density of poly fill. Back-end-of-line (BEOL) or interconnect sensitive structures enable examination of variation in dielectric or metal thickness at different metal levels and impact on interconnect capacitance.The second key element of the test structure methodology is a scan-chain architecture enabling independent operation and readout of replicated ring oscillator test structures. In this second version test chip, designed and fabricated in $0.25 m technology, over 2000 ring oscillators per chip can be measured using simple digital control and readout circuitry interfaced to the packaged chip. The scan chain approach involves reading in a control word to each ring oscillator, which specifies if that oscillator is to operate and if the RO frequency is to be put onto an output bus into frequency division and output circuitry. Additional test chip design elements include separate ring oscillator and control logic power grids, so that the frequency dependence of the ring oscillators on power supply voltage can also be measured, enabling separation of channel length and threshold voltage variation contributions.A $0.25 µm version of the test chip has been fabricated, and measurement and statistical analysis of 35 chips have been successfully conducted. Results indicate that within-wafer variation continues to be larger than within-chip variation; however, systematic spatial patterns and layout-dependent variations within the chip are substantial and of particular concern in timing (which depends on matched signal delays across a chip or logic block). The test chip can be ported to other advanced technologies to provide information on layout-dependent and spatially-dependent process variation sour","PeriodicalId":338381,"journal":{"name":"TAU '02","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129004933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The statistical longest path problem and its application to delay analysis of logical circuits","authors":"Ei Ando, M. Yamashita, Toshio Nakata, Y. Matsunaga","doi":"10.1145/589411.589440","DOIUrl":"https://doi.org/10.1145/589411.589440","url":null,"abstract":"This paper presents an algorithm for estimating, in the sense below, the length of a longest path of a given directed acyclic graph (DAG) whose edge lengths are given as random variables with normal distributions. Let <i>F</i>(<i>x</i>) be the distribution function of the length of a longest path of a given DAG. The algorithm computes a normal distribution function &Ftilde;(<i>x</i>) such that ˜F(<i>x</i>) 〈 <i>F</i>(<i>x</i>) if <i>F</i>(<i>x</i>) 〉 <i>a</i>, given a constant <i>a</i> (0.5 〈 <i>a</i> 〈 1.0). We conduct two experiments to demonstrate the accuracy of &Ftilde;(<i>x</i>).","PeriodicalId":338381,"journal":{"name":"TAU '02","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115527062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A library compatible driving point model for on-chip RLC interconnects","authors":"K. Agarwal, D. Sylvester, D. Blaauw","doi":"10.1145/589411.589425","DOIUrl":"https://doi.org/10.1145/589411.589425","url":null,"abstract":"This paper presents a new library compatible approach to gate-level timing characterization in the presence of RLC interconnect loads. We describe a two-ramp model based on transmission line theory that accurately predicts both the 50% delay and waveform shape (slew rate) at the driver output when inductive effects are significant. The approach does not rely on piecewise linear Thevenin voltage sources. It is compatible with existing library characterization methods and is computationally efficient. Results are compared with SPICE and demonstrate typical errors under 10% for both delay and slew rate.","PeriodicalId":338381,"journal":{"name":"TAU '02","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121335244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reducing probabilistic timed petri nets for asynchronous architectural analysis","authors":"Sangyun Kim, Sunan Tugsinavisut, P. Beerel","doi":"10.1145/589411.589441","DOIUrl":"https://doi.org/10.1145/589411.589441","url":null,"abstract":"This paper introduces structural reductions of probabilistic timed Petri nets that preserve a large class of performance measurements. In particular, the paper proposes a class of reductions that preserve efficiently computable bounds of statistics of time-separation of events (TSEs). It identifies two specific reductions within this class. It demonstrates the utility of these reductions by reducing a detailed Petri net describing the four-phase protocol of a well-known asynchronous pipeline template into a simpler two-phase architectural-level Petri net model. The benefit of this reduced model is that the run-time of subsequent TSE analysis can be greatly improved.","PeriodicalId":338381,"journal":{"name":"TAU '02","volume":"246 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113980794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Minimum-power retiming for dual-supply CMOS circuits","authors":"F. Sheikh, A. Kuehlmann, K. Keutzer","doi":"10.1145/589411.589422","DOIUrl":"https://doi.org/10.1145/589411.589422","url":null,"abstract":"The use of dual-supply voltages at the gate level is an effective technique to limit dynamic power consumption while preserving performance. However, its use in commercial circuit designs is limited primarily due to lack of CAD tool support. Very little work has been carried out to leverage multiple supply voltages for timing, area, and power trade-offs during logic synthesis. This paper describes an extension to the retiming framework which is leveraged to synthesize low-power CMOS circuits using dual-supply voltages. A mathematical formulation of the problem is presented with the central objective to minimize dynamic power while maintaining the target clock period.","PeriodicalId":338381,"journal":{"name":"TAU '02","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125048992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew","authors":"B. Taskin, I. Kourtev","doi":"10.1145/589411.589437","DOIUrl":"https://doi.org/10.1145/589411.589437","url":null,"abstract":"This paper describes a linear programming (LP) formulation for performance optimization of large-scale, synchronous circuits with level-sensitive latches. The proposed formulation permits circuits to operate at a higher clock frequency---that is, with a lower clock period---by the application of both non-zero clock skew scheduling [7] and time borrowing [9]. This LP formulation is computationally efficient and demonstrates significant circuit performance improvement. Unlike the approach documented in [2], the LP model of the clock period minimization problem presented here is stand-alone and independent of the specific LP solver (solution algorithm) used. The modified big M (MBM) method is introduced and applied to the linearization of the non-linear timing constraints of level-sensitive circuits into a solvable set of fully linear constraints. Clock period improvements as large as 63% are demonstrated over conventional flip-flop based circuits with zero clock skew. These improvements are shown on the ISCAS'89 benchmark circuits by using the industrial linear solver CPLEX [1].","PeriodicalId":338381,"journal":{"name":"TAU '02","volume":"432 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132724589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quadratic deferred-merge embedding algorithm for zero skew clock distribution network","authors":"H. Saaied, D. Al-Khalili, A. Al-Khalili, M. Nekili","doi":"10.1145/589411.589438","DOIUrl":"https://doi.org/10.1145/589411.589438","url":null,"abstract":"Design of clock distribution networks (CDNs) in SoCs is one of the critical aspects in the realization of high performance products. Traditionally, the CDNs are generated based on binary tree data structure. However, this approach has it own limitations in terms of silicon utilization, power dissipation and latency. In this paper we propose to migrate to a quadrature tree data structure in order to gain more flexibility in locating the Steiner nodes, that can be used to minimize the CDN wire length. The quadratic data structure is applied to the Deferred-Merge Embedding algorithm (DME) where the results show that the total wire length of the CDN can be reduced effectively as the number of clock pins increases. For CDNs of 256, 1024, 4096, 16384 and 65536 clock pins, the proposed technique can reduce the CDNs total wire length by 1.85%, 3.48%, 9.2%, 23.7% and 40.3% respectively with an insignificant increase in run time. Also, using the Quadratic structure helped reducing the clock delay and the total wire elongation lengths required to achieve Zero Skew CDN.","PeriodicalId":338381,"journal":{"name":"TAU '02","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123483946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Active shielding of RLC global interconnects","authors":"Himanshu Kaul, D. Sylvester, D. Blaauw","doi":"10.1145/589411.589431","DOIUrl":"https://doi.org/10.1145/589411.589431","url":null,"abstract":"In this paper we apply the concept of active shielding to inductive global interconnections. Active shields, which are shield wires that are switched at the same time as the signal wire, were initially developed to speed global signal propagation in RC dominated lines by ensuring in-phase switching of adjacent nets. This work further investigates this concept by examining RLC wiring. We find a distinct line width crossover point at which in-phase switching of neighbors no longer offers benefits and where the increased inductive behavior introduces substantial ringing. We propose the use of out-of-phase active shielding for such wide inductive lines. This technique is shown to significantly reduce ringing behavior (up to 4.5X) and offer better slopes (up to 40% reduction) and signal propagation delays, all of which are shown in the context of a clock net optimization.","PeriodicalId":338381,"journal":{"name":"TAU '02","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128878812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"PERI: a technique for extending delay and slew metrics to ramp inputs","authors":"Chandramouli V. Kashyap, C. Alpert, Frank Liu, A. Devgan","doi":"10.1145/589411.589424","DOIUrl":"https://doi.org/10.1145/589411.589424","url":null,"abstract":"Recent years have seen significant research in finding closed-form formulae for the delay of an RC circuit that improves upon the Elmore delay model. However, several of these formulae assume a step excitation, leaving it to the reader to find a suitable extension to ramp inputs. The few works that do consider ramp inputs do not present a closed-form formula that works for a wide range of possible input slews. We propose a new technique, PERI (Probability distribution function Extension for Ramp Inputs), that extends delay metrics for step inputs to the more general and realistic non-step (such as a saturated ramp) inputs. Although there has been little work done in finding good slew (which is also referred as signal transition time) metrics, we also show how one can extend a slew metric for step inputs to the non-step case. We validate the efficacy of our approach through experimental results from several hundred RC dominated nets extracted from an industry ASIC design.","PeriodicalId":338381,"journal":{"name":"TAU '02","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115781675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}