TAU '02Pub Date : 2002-12-02DOI: 10.1145/589411.589433
B. Floyd, Xiaoling Guo, J. Caserta, T. Dickson, C. Hung, Kihong Kim, K. O. Kenneth
{"title":"Wireless interconnects for clock distribution","authors":"B. Floyd, Xiaoling Guo, J. Caserta, T. Dickson, C. Hung, Kihong Kim, K. O. Kenneth","doi":"10.1145/589411.589433","DOIUrl":"https://doi.org/10.1145/589411.589433","url":null,"abstract":"A wireless interconnect system for clock distribution which transmits and receives microwave signals across a chip using integrated antennas, receivers, and transmitters is presented. All of the com-ponents of the system are demonstrated at 15 GHz in a 0.18-m CMOS technology. Wireless interconnection is achieved over a distance of 5.6 mm.","PeriodicalId":338381,"journal":{"name":"TAU '02","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114138620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
TAU '02Pub Date : 2002-12-02DOI: 10.1145/589411.589439
P. Pénzes, M. Nyström, Alain J. Martin
{"title":"Transistor sizing of energy-delay--efficient circuits","authors":"P. Pénzes, M. Nyström, Alain J. Martin","doi":"10.1145/589411.589439","DOIUrl":"https://doi.org/10.1145/589411.589439","url":null,"abstract":"This paper studies the problem of transistor sizing of CMOS circuits optimized for energy-delay efficiency, i.e., for optimal Etn where E is the energy consumption and t is the delay of the circuit, while n is a fixed positive optimization index that reflects the chosen trade-off between energy and delay.We propose a set of analytical formulas that closely approximate the optimal transistor sizes. We then study an efficient iteration procedure that can further improve the original analytical solution. Based on these results, we introduce a novel transistor sizing algorithm for energy-delay efficiency.","PeriodicalId":338381,"journal":{"name":"TAU '02","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116991456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}