Minimum-power retiming for dual-supply CMOS circuits

The use of dual-supply voltages at the gate level is an effective technique to limit dynamic power consumption while preserving performance. However, its use in commercial circuit designs is limited primarily due to lack of CAD tool support. Very little work has been carried out to leverage multiple supply voltages for timing, area, and power trade-offs during logic synthesis. This paper describes an extension to the retiming framework which is leveraged to synthesize low-power CMOS circuits using dual-supply voltages. A mathematical formulation of the problem is presented with the central objective to minimize dynamic power while maintaining the target clock period.