A probabilistic approach to clock cycle prediction

When developing new technologies, it is important to have an indication of the gain that can be achieved by exploring different research directions. Part of this gain is measured by achievable system performance. In this paper, we focus on the a priori prediction of clock speed as a measure for system performance.Previous approaches to clock cycle prediction were based on the summation of a number of (predicted) wire delays, equal to the maximum logic depth in a circuit. However, these methods do not consider the fact that the minimum clock cycle is determined by the largest combinatorial delay that occurs in a very complex and parallel interconnection topology. Indeed, in most circuits, there are a large number of paths with maximum or almost maximum logic depth. When implementing those circuits, any of these paths might become the path with maximal delay.In this paper, we present a new probabilistic model for predicting the maximal combinatorial path delay that partially captures the impact of the parallelism, present in real circuits. Our model is based on the distributions of the sum and of the maximum of a number of independent random variables. We experimentally validate our model using measured wire delay distributions.