Clock schedule verification with crosstalk

Abstract

Delay variation due to crosstalk has made timing analysis a hard problem. In sequential circuits with transparent latches, crosstalk makes the clock schedule verification even harder. In this paper, we point out a false negative problem in current clock schedule verification techniques and propose a new approach based on switching windows. In this approach, coupling delay calculations are naturally combined with latch iterations. A novel algorithm is given for clock schedule verification in the presence of crosstalk and primary experiments show promising results.