Worst case clock skew under power supply variations

Abstract

On-chip power distribution networks are resistive in nature and hence create large variations in the voltage levels across the chip. These variations have significant impact on the delays of global signals, such as the clock, which span the entire chip. A clock network that is balanced without considering delay variations induced by power supply variations can suffer significant degradation of its skew during the chips operation. In this paper, we describe a practical approach to determining the worst-case skew in a clock network in the presence of power supply variations. Experiments using the proposed approach on the clock nets of several processors show that clock skew can nearly double in the worst case. The proposed methodology is easily extendable for studying the impact of process variations and on-chip parasitic inductance on clock skew.