2020 European Conference on Circuit Theory and Design (ECCTD)最新文献_第4页

An Overview of Automatic Antenna Impedance Matching for Mobile Communications 移动通信天线阻抗自动匹配技术综述

2020 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2020-09-01 DOI: 10.1109/ECCTD49232.2020.9218350

D. Lauder, Yichuang Sun

引用次数: 0

Implementation and Optimization of Chemical Logic Gates Using Memristive Cellular Automata 基于记忆元胞自动机的化学逻辑门的实现与优化

2020 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2020-09-01 DOI: 10.1109/ECCTD49232.2020.9218330

Iosif-Angelos Fyrigos, V. Ntinas, Michail-Antisthenis I. Tsompanas, Stavros Kitsios, G. Sirakoulis, D. Tsoukalas, A. Adamatzky

{"title":"Implementation and Optimization of Chemical Logic Gates Using Memristive Cellular Automata","authors":"Iosif-Angelos Fyrigos, V. Ntinas, Michail-Antisthenis I. Tsompanas, Stavros Kitsios, G. Sirakoulis, D. Tsoukalas, A. Adamatzky","doi":"10.1109/ECCTD49232.2020.9218330","DOIUrl":"https://doi.org/10.1109/ECCTD49232.2020.9218330","url":null,"abstract":"By utilizing biologically inspired approaches, a wide range of complex and computationally intensive problems can be transformed to simpler and more appropriate forms to be easily solved by unconventional computing systems. A well-known computing platform with such characteristics is the Cellular Automata paradigm, where a spatial-extended network of nodes, with local interactions, exhibit emerging computations. In such CA networks, the application of nanodevices, like memristors, with inherent novel abilities, like memory storing and computing capabilities, together with nonlinear interactions is promising for the advancement of computation. In this work, a memristor-based Cellular Automaton (MemCA) is developed for the implementation and optimization of topological chemical logic gates. The proposed MemCA is inspired by the behaviour of the biological organism Physarum Polycephalum that firstly spreads to reach nutrients in its environment and afterwards shrinks to optimize its energy requirements, while performing biochemical oscillations to accomplish these tasks. In a similar way, the MemCA simulates Physarum's spreading to perform the spatial operation of the chemical logic gate, while Physarum's shrinking was utilised to further optimise the required area of the gate.","PeriodicalId":336302,"journal":{"name":"2020 European Conference on Circuit Theory and Design (ECCTD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124481759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Integer Convolutional Neural Networks with Boolean Activations: The BoolHash Algorithm 布尔激活的整数卷积神经网络:BoolHash算法

2020 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2020-09-01 DOI: 10.1109/ECCTD49232.2020.9218306

Grigor Gatchev, V. Mollov

引用次数: 2

Improving Aliasing Rejection by Inserting Additional Zeros into Folding Bands Using Simple Filters 通过使用简单滤波器在折叠带中插入额外的零来改善混叠抑制

2020 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2020-09-01 DOI: 10.1109/ECCTD49232.2020.9218403

G. Jovanovic-Dolecek, L. Dolecek

引用次数: 0

Multylayer perceptron representation by index matrices with elements in a fixed interval 用元素在固定区间的索引矩阵表示多层感知器

2020 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2020-09-01 DOI: 10.1109/ECCTD49232.2020.9218374

Krassimir Atanasov, S. Sotirov

引用次数: 1

A Low-Power Wide Supply Range Delay-Line Based IC for Amperometric Measurement 基于低功耗宽供电范围延迟线的安培测量集成电路

2020 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2020-09-01 DOI: 10.1109/ECCTD49232.2020.9218415

A. Nag, R. Dahiya, S. Mitra

引用次数: 1

A Flipping Active-Diode Rectifier for Piezoelectric-Vibration Energy-Harvesting 一种用于压电振动能量收集的翻转有源二极管整流器

2020 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2020-09-01 DOI: 10.1109/ECCTD49232.2020.9218313

Wan-Ling Wu, Ching-Yuan Yang, Dung-An Wang

引用次数: 4

Design of Area-Efficient Physical Unclonable Functions Derived From CNNs: Trade-Offs and Optimization 基于cnn的面积高效物理不可克隆函数的设计:权衡与优化

2020 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2020-09-01 DOI: 10.1109/ECCTD49232.2020.9218316

T. Addabbo, A. Fort, Riccardo Moretti, M. Mugnaini, Hadis Takaloo, V. Vignoli

引用次数: 2

A Simulation Tool for Analysis of Oscillator Ensembles Defined by Kuramoto Model 基于Kuramoto模型的振子系综分析仿真工具

2020 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2020-09-01 DOI: 10.1109/ECCTD49232.2020.9218382

M. Gourary, S. Rusakov

引用次数: 2

Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process 基于28nm CMOS工艺的1.5 GHz低抖动DCO环设计

2020 European Conference on Circuit Theory and Design (ECCTD) Pub Date : 2020-09-01 DOI: 10.1109/ECCTD49232.2020.9218352

P. Bisiaux, E. Blokhina, Eugene Koskin, T. Siriburanon, D. Galayko

{"title":"Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process","authors":"P. Bisiaux, E. Blokhina, Eugene Koskin, T. Siriburanon, D. Galayko","doi":"10.1109/ECCTD49232.2020.9218352","DOIUrl":"https://doi.org/10.1109/ECCTD49232.2020.9218352","url":null,"abstract":"The immunity of jitter with respect to supply voltage is one of the desirable characteristics of digitally controlled oscillators (DCO) for clocking applications. This paper presents a design of such an oscillator with a high frequency resolution and small area in 28 nm technology. In order to reduce the dependence of the oscillator frequency on its voltage supply, differential amplifiers are used as inverters (delay cells) and a bias circuit with a stable voltage output is employed to bias the oscillator. From post-layout simulations, this DCO achieves a dynamic range from 1.13 to 1.54 GHz with the use of differential delay cells, the variation of the output frequency is less than 4.5% over all the frequency range, for VDD variation of 10%. The frequency control has 9.2 bits, giving an average frequency step of 722 kHz. This DCO achieves a phase noise of -74 dBc/Hz@1MHz or an jitter equivalence of 2.3 ps. The maximal power consumption of this DCO at maximum frequency is 840 μW, which is a low figure comparing to the state-of-the-art implementation with typical power of sub-milliwatts for the similar frequency range.","PeriodicalId":336302,"journal":{"name":"2020 European Conference on Circuit Theory and Design (ECCTD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126747351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1