Design of Area-Efficient Physical Unclonable Functions Derived From CNNs: Trade-Offs and Optimization

Abstract

We discuss the design of an area-efficient CMOS analog core-cell implementing a PUF derived from a two-neurons Cellular Neural Network (CNN). The study is based on both theoretical modeling and numerical simulations, proposing circuit solutions in which the area consumption is strongly reduced by eliminating state capacitors and relying on distributed parasitic capacitances only.