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Generating power-optimal standard cell library specification using neural network technique 利用神经网络技术生成功率最优标准单元库规范
2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2017-10-01 DOI: 10.1109/PRIMEASIA.2017.8280374
S. Lim, Y. W. Lim, S. Mashohor, N. Kamsani, R. Sidek, S. J. Hashim, F. Rokhani
{"title":"Generating power-optimal standard cell library specification using neural network technique","authors":"S. Lim, Y. W. Lim, S. Mashohor, N. Kamsani, R. Sidek, S. J. Hashim, F. Rokhani","doi":"10.1109/PRIMEASIA.2017.8280374","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280374","url":null,"abstract":"In VLSI semi-custom design approach, power-optimal standard cell library selection for a given block design requires time-consuming iterative processes. This paper presents a framework to select a standard cell library that can result in near-optimal power while satisfying targeted frequency. The framework relies on neural network model to quickly predict the total power of a block design associated with a given standard cell library in order to speed up the synthesis process. The experimental result based on various synthesized benchmark circuits demonstrated the effectiveness of proposed framework for near-optimal standard cell library specification.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117218774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A CMOS 180nm class-AB power amplifier with intergrated phase linearizer for BLE 4.0 achieving 11.5dB gain, 38.4% PAE and 20dBm OIP3 一种集成相位线性器的180nm ab类CMOS功率放大器，可实现11.5dB增益，38.4% PAE和20dBm OIP3
2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2017-10-01 DOI: 10.1109/PRIMEASIA.2017.8280364
Premmilaah Gunasegaran, J. Rajendran, H. Ramiah
{"title":"A CMOS 180nm class-AB power amplifier with intergrated phase linearizer for BLE 4.0 achieving 11.5dB gain, 38.4% PAE and 20dBm OIP3","authors":"Premmilaah Gunasegaran, J. Rajendran, H. Ramiah","doi":"10.1109/PRIMEASIA.2017.8280364","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280364","url":null,"abstract":"In this paper, the design of a low power consumption linear power amplifier (PA) for Bluetooth Low Energy (BLE) application is presented. A passive linearizer is integrated at the input of the CMOS PA to nullify the effect of the Cgs capacitance thus improving the linearity and efficiency without trading-off the power gain and stability. The PA delivers more than 10dB power gain from 2.4GHz to 2.5GHz. At centre frequency of 2.45GHz, the PA exhibits gain of 11.5dB with corresponding PAE of 38.4% and maximum output power of 15dBm followed by OIP3 of 20.3dBm. This performance is achieved with supply voltage headroom of 1.8V. The proposed linearization scheme serves to be a good solution to improve the linear output power of a CMOS PA without trading off other critical parameters.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123732782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Area-efficient CMOS implementation of NCL gates for XOR-AND/OR dominated circuits 为异或与或控制电路的面积高效的NCL门的CMOS实现
2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2017-10-01 DOI: 10.1109/PRIMEASIA.2017.8280358
Aileen B. Caberos, Shu-Chuan Huang, Fu-Chiung Cheng
{"title":"Area-efficient CMOS implementation of NCL gates for XOR-AND/OR dominated circuits","authors":"Aileen B. Caberos, Shu-Chuan Huang, Fu-Chiung Cheng","doi":"10.1109/PRIMEASIA.2017.8280358","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280358","url":null,"abstract":"Null conventional logic units are the most important logic units in asynchronous circuits. This paper presents an area-efficient CMOS implementation of Null Conventional Logic (NCL) gates for XOR-AND/OR dominated asynchronous circuits. These optimization of logic gates are based on Binary Decision Diagram (BDD) that produces 25% and 14.29% fewer transistor counts for the proposed logic topology of XOR and AND/OR respectively. Thus, giving a reduced area of more than 14% compared with the conventional NCL logic circuits. The simulation results show the delay and energy consumption can give a reasonable result as compared to conventional approach.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132344932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Switching power control for multimode multiband power amplifier 多模多频带功率放大器的开关功率控制
2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2017-10-01 DOI: 10.1109/PRIMEASIA.2017.8280379
Veeraiyah Thangasamy, N. Kamsani, T. Zulkifli
{"title":"Switching power control for multimode multiband power amplifier","authors":"Veeraiyah Thangasamy, N. Kamsani, T. Zulkifli","doi":"10.1109/PRIMEASIA.2017.8280379","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280379","url":null,"abstract":"Driven by ever-increasing consumer demand for wireless devices capable of supporting multiple air standards and applications, the implementation of multimode multiband (MMMB) power amplifier (PA) has been steadily increasing. This paper presents a design of a MMMB PA based on an industry-standard 130nm CMOS process technology, capable of operating in three power modes and in three different bands. Multiple gated transistor technique (MTGR) has been designed whereby the output power from the PA is controlled by external switching control voltage. Series combining transformer has been to adopted to achieve higher output power. The PA has 300MHz bandwidth starting from the frequency of 1.7GHz up to 2.0GHz, covering the LTE bands 1, 2 and 3, with output saturated power of 33dBm.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133403666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Proposing an enhanced approach of threshold voltage extraction for nano MOSFET 提出了一种改进的纳米MOSFET阈值电压提取方法
2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2017-10-01 DOI: 10.1109/PRIMEASIA.2017.8280350
Yashu Swami, Sanjeev Rai
{"title":"Proposing an enhanced approach of threshold voltage extraction for nano MOSFET","authors":"Yashu Swami, Sanjeev Rai","doi":"10.1109/PRIMEASIA.2017.8280350","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280350","url":null,"abstract":"Precise threshold voltage value is evaluated by several estimation techniques. The governing gauge for efficient threshold voltage definition and extraction method can be itemized as clarity, simplicity, precision, and stability throughout the operating conditions and technology nodes. The values diverge due to various short channel effects (SCE), second order effects and non-idealities present in the device. A new enhanced approach for defining and extracting the threshold voltage for nano MOSFET is presented in the manuscript. The SCE independent threshold voltage extraction approach named Hybrid Extrapolation Vth Extraction Method (HEEM) is elaborated, modeled and compared with other prevalent threshold voltage extraction methods for validation of the results. The results are demonstrated by extensive 2-D TCAD simulation and confirmed analytically at various technology nodes.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125108067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Preliminary results of electrical characterization of GO towards MCF7 and MCF10a at different concentrations 不同浓度下氧化石墨烯对MCF7和MCF10a的电特性初步结果
2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2017-10-01 DOI: 10.1109/PRIMEASIA.2017.8280372
L. F. A. Talip, S. S. Isa, M. M. Ramli, N. Mazlan, D. Halin, Rafeezul Mohamed, M. N. Mohtar
{"title":"Preliminary results of electrical characterization of GO towards MCF7 and MCF10a at different concentrations","authors":"L. F. A. Talip, S. S. Isa, M. M. Ramli, N. Mazlan, D. Halin, Rafeezul Mohamed, M. N. Mohtar","doi":"10.1109/PRIMEASIA.2017.8280372","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280372","url":null,"abstract":"GO is the 2D carbon sheet with additional functional groups, is more stable in various solvents, easy to be produced and manipulated especially in biological system. At the moment, GO is only utilized as the drug delivery agent during treatment. In this study, the resistivity of GO towards breast cancer cell (MCF7) and normal breast cell (MCF10a) using interdigitated electrodes (IDE) were investigated. The interaction of different concentrations of GO as the sensing material on the tested cells which act as analyte can change electrical response. The tested cell were treated with six different concentrations of GO and was dropped to the IDE with different period of time in order to examine electrical behavior. For MCF10a, at high concentration the resistances of MCF10 remain in the same order of magnitude with increasing time of detection while for MCF7 at high concentration, the resistances were greatly influenced by the time of detection where the value significantly changed after 5 minutes and 10 minutes. The number of viable cell does not give effect to the resistance.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126350307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Integrated Class C-VCO — Mixer for 2.45 GHz transmitter in 180nm CMOS technology 集成类C-VCO混频器2.45 GHz发射机在180nm CMOS技术
2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2017-10-01 DOI: 10.1109/PRIMEASIA.2017.8280367
P. Shasidharan, H. Ramiah, J. Rajendran
{"title":"Integrated Class C-VCO — Mixer for 2.45 GHz transmitter in 180nm CMOS technology","authors":"P. Shasidharan, H. Ramiah, J. Rajendran","doi":"10.1109/PRIMEASIA.2017.8280367","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280367","url":null,"abstract":"This paper presents on the Up-conversion mixer and Class-C CMOS LC VCO which operates at 2.45 GHz designed using 180 nm CMOS RF Technology. Voltage Controlled Oscillator, VCO combined with mixer design and achieves phase noise of −119 dBc/Hz and −131 dBc/Hz at 1 MHz and 3 MHz offset respectively. The system consumes 2.04 mW from 1.2 V supply. The measured Figure of Merit (FoM) reaches 182.08 dBc/Hz at 1 MHz offset. The passive mixer recorded third-order input intercept point (IIP3) of 13.28 dBm and 1-dB compression point (P1dB) of 5.17 dBm. This mixer design generates a stable matching at −23.91 dB and achieves a good port to port isolation of −61 dB.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121508381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Moderate traumatic brain injury identification for MEG data using PU (Positive and Unseen) learning 使用PU (Positive and Unseen)学习识别中度创伤性脑损伤的MEG数据
2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2017-10-01 DOI: 10.1109/PRIMEASIA.2017.8280355
Waqas Rasheed, M. Bhatti, N. Hisham bin Hamid, T. Tang, Z. Idris
{"title":"Moderate traumatic brain injury identification for MEG data using PU (Positive and Unseen) learning","authors":"Waqas Rasheed, M. Bhatti, N. Hisham bin Hamid, T. Tang, Z. Idris","doi":"10.1109/PRIMEASIA.2017.8280355","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280355","url":null,"abstract":"Traumatic brain injury (TBI) is a source of disability and morbidity worldwide. Mild cognitive impairment (MCI) and mild TBI cause functional connectivity interruption for a very limited time frame; however, the patient diagnosed with moderate to severe forms of TBI requires quick, hassle free and precise identification of functional deficits in order to provide timely care. Magnetoencephalography (MEG) is the neuroimaging modality that provides the required information, and is useful for non-contact recording of functional connectivity assessment of TBI subjects. Default mode network (DMN) has been studied and described using functional magnetic resonance imaging (fMRI). This paper proposes a method to develop a default model of biomagnetic activations, as sensed over cortical region using MEG scans. The model is used to classify and assess TBI subjects. The classification is performed by devising default coherence limits between all pairs of MEG sensors for positive (control) group, and the assessment of severity is carried out by using PU learning method (single class model), where P (positive) data is from control population is utilized to compute significant functional connectivity deficits.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123704020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Optimised completion detection circuits for null convention logic pipelines 零约定逻辑管线完井检测电路优化
2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2017-10-01 DOI: 10.1109/PRIMEASIA.2017.8280353
P. Dabholkar, P. Beckett
{"title":"Optimised completion detection circuits for null convention logic pipelines","authors":"P. Dabholkar, P. Beckett","doi":"10.1109/PRIMEASIA.2017.8280353","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280353","url":null,"abstract":"Null Convention Logic is a Quasi Delay Insensitive asynchronous design technique which requires special completion detection circuits that span the width of the data path to control the timing and ensure correct operation. These circuits occupy a large area on the chip and their propagation delay greatly affects the throughput of the system. In this paper, we propose a few improved techniques for implementing these completion detection circuits. Instead of designing the circuit using template-based NCL threshold gates, we simplify and merge the gates and route complementary Data and Null values as appropriate to ensure correct operation. Optimizing transistor sizes to achieve equal propagation delays in both the Data-Null and Null-Data transitions results in an area saving of over 30% and an energy saving of about 50% compared to conventional completion circuits. A further modification to the THxx gate circuit is shown that merges the Hold and Drive sections of the circuit to create a smaller, more balanced gate with better performance.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114170729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Frustrated coupled oscillators with anomalous coupling method 采用异常耦合方法的受挫耦合振子
2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2017-10-01 DOI: 10.1109/PRIMEASIA.2017.8280357
K. Ueta, Y. Uwate, Y. Nishio
{"title":"Frustrated coupled oscillators with anomalous coupling method","authors":"K. Ueta, Y. Uwate, Y. Nishio","doi":"10.1109/PRIMEASIA.2017.8280357","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2017.8280357","url":null,"abstract":"Synchronization phenomena of frustration network by coupled oscillators has been studied in a wide range of fields, such as medicine and engineering. It is investigated towards various systems up to now. However, analysis of regarding more complex systems are little. In our study, we developed the system model so that a basic minimum unit even in more complex systems. In addition, we observed synchronization phenomena about the system. In this paper, we show the result of circuit experiment with oscilloscope. Finally, we state the conclusion accompanying the experiment results.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"331 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123311969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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