Area-efficient CMOS implementation of NCL gates for XOR-AND/OR dominated circuits

Null conventional logic units are the most important logic units in asynchronous circuits. This paper presents an area-efficient CMOS implementation of Null Conventional Logic (NCL) gates for XOR-AND/OR dominated asynchronous circuits. These optimization of logic gates are based on Binary Decision Diagram (BDD) that produces 25% and 14.29% fewer transistor counts for the proposed logic topology of XOR and AND/OR respectively. Thus, giving a reduced area of more than 14% compared with the conventional NCL logic circuits. The simulation results show the delay and energy consumption can give a reasonable result as compared to conventional approach.