一种集成相位线性器的180nm ab类CMOS功率放大器，可实现11.5dB增益，38.4% PAE和20dBm OIP3

2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2017-10-01 DOI:10.1109/PRIMEASIA.2017.8280364

Premmilaah Gunasegaran, J. Rajendran, H. Ramiah

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引用次数: 8

摘要

本文设计了一种低功耗线性功率放大器，用于低功耗蓝牙(BLE)应用。在CMOS PA的输入端集成了一个无源线性器，以消除Cgs电容的影响，从而在不牺牲功率增益和稳定性的情况下提高线性度和效率。扩音器在2.4GHz至2.5GHz范围内提供超过10dB的功率增益。在中心频率为2.45GHz时，放大器的增益为11.5dB，相应的PAE为38.4%，最大输出功率为15dBm, OIP3为20.3dBm。这种性能是在电源电压净空为1.8V的情况下实现的。提出的线性化方案是一个很好的解决方案，以提高CMOS放大器的线性输出功率，而不牺牲其他关键参数。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A CMOS 180nm class-AB power amplifier with intergrated phase linearizer for BLE 4.0 achieving 11.5dB gain, 38.4% PAE and 20dBm OIP3

In this paper, the design of a low power consumption linear power amplifier (PA) for Bluetooth Low Energy (BLE) application is presented. A passive linearizer is integrated at the input of the CMOS PA to nullify the effect of the Cgs capacitance thus improving the linearity and efficiency without trading-off the power gain and stability. The PA delivers more than 10dB power gain from 2.4GHz to 2.5GHz. At centre frequency of 2.45GHz, the PA exhibits gain of 11.5dB with corresponding PAE of 38.4% and maximum output power of 15dBm followed by OIP3 of 20.3dBm. This performance is achieved with supply voltage headroom of 1.8V. The proposed linearization scheme serves to be a good solution to improve the linear output power of a CMOS PA without trading off other critical parameters.

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2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)

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