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Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)最新文献

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A method for approximate equivalence checking 近似等价检验的一种方法
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848656
M. Thornton, R. Drechsler, Wolfgang Günther
{"title":"A method for approximate equivalence checking","authors":"M. Thornton, R. Drechsler, Wolfgang Günther","doi":"10.1109/ISMVL.2000.848656","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848656","url":null,"abstract":"An approximate equivalence checking method is developed based on the use of partial Haar spectral diagrams (HSDs). Partial HSDs are defined and used to represent a subset of the Haar spectral coefficients for two functions. Due to the uniqueness properties of the Haar transform, a necessary condition for equivalence is that the individual coefficients must have the same value. The probability that two-functions are equivalent is then computed based on the number of observed, same-valued, Haar coefficients. The method described here can be useful for the case where two candidate functions require extreme amounts of computational resources for exact equivalence checking. For simplicity, the technique is explained for the binary case first and extensions to Multiple Valued Logic (MVL) are shown afterwards. Experimental results are provided to validate the effectiveness of this approach.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114544369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Evolvable hardware: from on-chip circuit synthesis to evolvable space systems 可进化硬件:从片上电路合成到可进化空间系统
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848615
A. Stoica
{"title":"Evolvable hardware: from on-chip circuit synthesis to evolvable space systems","authors":"A. Stoica","doi":"10.1109/ISMVL.2000.848615","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848615","url":null,"abstract":"Evolvable Hardware (EHW) refers to HW design and self-reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, comments on selected applications, and presents a perspective on the development of the field. A fine-grained Field Programmable Transistor Array (FPTA) architecture for reconfigurable hardware is presented as an example of an initial effort toward evolution-oriented devices. Evolutionary experiments in simulations and with a FPTA chip in-the-loop demonstrate automatic synthesis of electronic circuits. Unconventional circuits, for which there are no textbook design guidelines, are particularly appealing to evolvable hardware. To illustrate this situation, one demonstrates here the evolution of circuits implementing parametrical connectives for fuzzy logics. In addition to synthesizing circuits for new functions, evolvable hardware can be used to preserve existing functions and achieve fault-tolerance, determining circuit configurations that circumvent the faults. These characteristics are extremely important for enabling spacecraft to survive harsh environments and to have long life. Expanding reconfiguration to other types of spacecraft hardcore (i.e. optics, MEMS, etc.) could lead to evolvable space systems.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125019529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
On the intersection of maximal partial clones and the join of minimal partial clones 极大偏克隆的交与极小偏克隆的联接
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848649
L. Haddad, Hajime Machida, I. Rosenberg
{"title":"On the intersection of maximal partial clones and the join of minimal partial clones","authors":"L. Haddad, Hajime Machida, I. Rosenberg","doi":"10.1109/ISMVL.2000.848649","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848649","url":null,"abstract":"Let A be a nonsingleton finite set and M be a family of maximal partial clones with trivial intersection over A. What is the smallest possible cardinality of M? Dually, if F is a family of minimal partial clones whose join is the set of all partial functions on A, then what is the smallest possible cardinality of F? The purpose of this note is to present results related to these two problems.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127935587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Mod-p decision diagrams: a data structure for multiple-valued functions Mod-p决策图:多值函数的数据结构
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848625
Harald Sack, E. Dubrova, C. Meinel
{"title":"Mod-p decision diagrams: a data structure for multiple-valued functions","authors":"Harald Sack, E. Dubrova, C. Meinel","doi":"10.1109/ISMVL.2000.848625","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848625","url":null,"abstract":"Multiple-valued decision diagrams (MDDs) give a way of approaching problems by using symbolic variables which are often more naturally associated with the problem statement than the variables obtained by a binary encoding. We present a more general class of MDDs, containing not only branching nodes but also functional nodes, labeled by addition modulo p operation, p-prime, and give algorithms for their manipulation Such decision diagrams have a potential of being more space-efficient than MDDs, However they are not a canonical representation of multiple-valued functions and thus the equivalence test of two Mod-p-DDs is more difficult then the test of two MDDs. To overcome this problem, we design a fast probabilistic equivalence test for Mod-p-DDs that requires time linear in the number of nodes.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116429660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Cost-analysis of 4-valued unary functions implemented using current-mode CMOS circuits 用电流型CMOS电路实现的4值一元函数的成本分析
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848622
M. Abd-El-Barr, A. Al-Mutawa
{"title":"Cost-analysis of 4-valued unary functions implemented using current-mode CMOS circuits","authors":"M. Abd-El-Barr, A. Al-Mutawa","doi":"10.1109/ISMVL.2000.848622","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848622","url":null,"abstract":"In this paper we consider the use of the incremental-cost approach for synthesis of 4-valued one-variable functions for implementation using current-mode CMOS (CMCL) circuits. One of the main features of CMCL circuits is the availability of currents flowing in both directions. This should add a degree of freedom which in turn facilitate the use of both positive and negative current values. Intermediate signed functions (both negative and positive) can then be readily available inside the circuits. In this paper we show that efficient use of signed intermediate functions can lead to substantial cost reduction, in terms of the number of devices needed for the implementation of functions. The results obtained using two techniques that use incremental-cost approach for synthesis of 4-valued one-variable functions for CMCL implementation and which use signed intermediate functions are presented and compared.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124388016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Computational neurobiology meets semiconductor engineering 计算神经生物学与半导体工程
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848593
D. Hammerstrom
{"title":"Computational neurobiology meets semiconductor engineering","authors":"D. Hammerstrom","doi":"10.1109/ISMVL.2000.848593","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848593","url":null,"abstract":"Many believe that the most important result to come out of the last ten years of neural network research is the significant change in perspective in the neuroscience community towards theory of computational neurobiology and functional neuro-models. Arriving on a fast moving train from the other direction is semiconductor technology, one of the greatest technology success stories of all time transistors are now approaching deep submicron (less than 100 nanometers) in size, and we will soon be building silicon chips with over 1 billion transistors. The marriage of these two technologies is creating what Andy Grove (ex-CEO of Intel) refers to as a strategic inflection point. Although previous attempts at merging these technologies were premature, silicon and computational neurobiology are now merging to create an extremely powerful, and radically new form of computation.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127151943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Rigidity problem of autodual clones 自对偶克隆的刚性问题
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848648
M. Miyakawa, I. Rosenberg
{"title":"Rigidity problem of autodual clones","authors":"M. Miyakawa, I. Rosenberg","doi":"10.1109/ISMVL.2000.848648","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848648","url":null,"abstract":"The rigidity problem for sets of autodual clones leads to two specific problems in clone theory: (i) What are the sets R of permutations of k={0, 1,..., k-1} such that 1) each r/spl isin/R has all cycles of the same prime length and 2) the only unary function on k which commutes with all elements of R is the identity e ? () If a clone C is the inter section of the autodual clones Pol r/sup /spl square//, r/spl isin/R and if it holds C/sup (1)/={e}, what is the least n such that C/sup (n)//spl sub//spl ang/J where J is the set of all projections ? We give some partial answers to these problems.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127159873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
de Morgan bisemilattices
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848616
J. Brzozowski
{"title":"de Morgan bisemilattices","authors":"J. Brzozowski","doi":"10.1109/ISMVL.2000.848616","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848616","url":null,"abstract":"We study de Morgan bisemilattices, which are algebras of the form (S, /spl cup/, /spl and/, /sup -/, 1, 0), where (S, /spl cup/, /spl and/) is a bisemilattice, 1 and 0 are the unit and zero elements of S, and /sup -/ is a unary operation, called quasi-complementation, that satisfies the involution law and de Morgan's laws. de Morgan bisemilattices are generalizations of de Morgan algebras, and have applications in multi-valued simulations of digital circuits. We present some basic observations about bisemilattices, and provide a set-theoretic characterization for a subfamily of de Morgan bisemilattices, which we call locally distributive de Morgan bilattices.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130895551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Evolutionary multi-level network synthesis in given design style 给定设计风格下的进化多级网络综合
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848628
T. Luba, C. Moraga, S. Yanushkevich, M. Opoka, V. Shmerko
{"title":"Evolutionary multi-level network synthesis in given design style","authors":"T. Luba, C. Moraga, S. Yanushkevich, M. Opoka, V. Shmerko","doi":"10.1109/ISMVL.2000.848628","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848628","url":null,"abstract":"This paper extends the technique of evolutionary network design. We study an evolutionary network design strategy from the position of design style. A hypothesis under investigation is that the uncertainty of a total search space (the space of all possible network solutions) through evolutionary network design is removed faster if this space is partitioned into subspaces. This idea has been realized through a parallel window-based scanning of these subspaces. Such a window is determined by the parameters of a multi-level network architecture in a given design style. Our approach allows to synthesize networks with more than two hundred quaternary gates. Moreover we show that information theoretical interpretation of the evolutionary process is useful, in particular in partitioning of network space and measuring of fitness function. The experimental data with 6-input quaternary and 11-inputs binary benchmarks demonstrate the efficiency of our program, EvoDesign, and an improvement against the recently obtained results.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132268892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Multi-input variable-threshold circuits for multi-valued logic functions 用于多值逻辑函数的多输入可变阈值电路
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) Pub Date : 2000-05-23 DOI: 10.1109/ISMVL.2000.848596
M. Syuto, Jing Shen, K. Tanno, O. Ishizuka
{"title":"Multi-input variable-threshold circuits for multi-valued logic functions","authors":"M. Syuto, Jing Shen, K. Tanno, O. Ishizuka","doi":"10.1109/ISMVL.2000.848596","DOIUrl":"https://doi.org/10.1109/ISMVL.2000.848596","url":null,"abstract":"In this paper, two-types of Multi-Input Variable-Threshold (M-I V-T) circuits and their applications to Multi-Valued Logic (MVL) are proposed. M-I V-T circuits are extensions of binary CMOS NAND and NOR gates to multi-valued logic. First, definitions of M-I V-T functions realized with M-I V-T circuits are presented, they are implemented using neuron-MOS transistors. The neuron-MOS transistor is a novel device with multi-input gates and can be fabricated by the standard CMOS process with a double-poly layer. Therefore, the proposed circuits can be easily fabricated by the standard CMOS process instead of using the multi-level ion implantation process. Second, the characteristics of the proposed circuits are evaluated using HSPICE simulations. Third, realization of a product term using M-I V-T circuits is presented. The circuit implementation of the product term is extended naturally from the literal circuit and is more powerful than the literal circuit. Finally, the synthesis of a MVL function with M-I V-T circuits is discussed.","PeriodicalId":334235,"journal":{"name":"Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130510162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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